The last decades of the semiconductor industry are characterized by exponential growth of functionality and number of transistors integrated in one piece of silicon. which is enabled through irnproving technology and smaller anel smaller device diInensions. Besides the perpetua.l challenges for further rniniaturization of elevices anel the complexity of integrateel circuits, a major obstacle arises in tenns of exponentia1 growth of costs for manufacturing anel design of integrateel circuits. One possible solution to these challenges is a new manufacturing anel design paradigrn for integrated circuits, which includes a nove1 device structure, the Vertical Slit Field Effect Transistor (VESFET), a new layout style anel manufacturing technology. The key concept of this paradigm is the use of identical unit sized devices placed into a regular array and the use of highly regular interconnects. The common objective is to reduce the costs and at the same time to maintain the performance and the design flexibility. This thesis investigates the circuit design aspects of the VESFET. First, the working principle of the VESFET and the elevice characteristics are eliscusseel. Second, the performance of VESFET based circuits is assesseel anel comparcd to state of the art 6,sn1n CMOS technology. In terms of elelay, the VESFET based circuits are competitive to CMOS but at the same time offer a bettet and lower energy-delay-product. A major focus of this work is dedicated to the independent gate control (IGC) of the inherent double gate structure of the VESFET. The IGC offers an increased flexibility to adjust properties of circuits. Further one can integrate an OR 01' AND functionality into one transistor, which allows to reduce the transistor count, corresponding to a reduction of the area, for logic circuits. IGC VESFET is a powerfulleverage for circuit designers to trade off speed, power and area of circuits. To dernonstrate the potential of the latter within larger circuit blocks, adder circuits are investigated. Layout studies with the new VESFET layout style are presenteel, which show that the transistor count reeluction with IGC VESFET also translates in a reeluced layout area with savings up to one third. For embedded SRA1,1 the IGC VESFET can be useel to increase the cell stability anel at the same time to maintain a good writeability.