For a heterogeneous environment where different CPU are assigned or performing different type of tasks requires some sort of performance assistance considering almost same type of resources. One possibility is to decouple the cache mechanism and to consider the usages of second level cache for every CPU to increase the performance and to make availability of common resources. This decoupling of memory significantly increases the performance by sharing and parallel reusing of the resources which is considered as the cache lines for multiple CPU at the same time to an embedded system. Of course, there arise considerably two issues to maintain for this implementation. One is to maintain the coherency of the data which implies that the CPU are dealing with the valid data which is consistent with that of existing in DDR and the second one is to design the whole thing considering the fixed bandwidth consideration of DDR or/and the bus system which is fixed for a subsystem.