Cantitate/Preț
Produs

Battery-aware Multiprocessor Task Scheduling

Autor Srobona Mitra, Anirban Lahiri, Anupam Basu
en Limba Engleză Paperback – 5 apr 2012
Battery life determines the duration and the extent of mobility for the battery-powered portable embedded systems and is a key performance metric for scheduling tasks on these multiprocessor systems. The main challenge is to space out the tasks to be executed on the multiprocessor system with the objective of shaping the battery discharge profile so as to enhance battery life, while at the same time, meeting the real-time timing constraints of the tasks. The current monograph addresses battery-aware static scheduling of precedence constrained task graphs with non-negligible intertask communication onto fully connected multiple processors in battery-powered mobile embedded systems. We propose a scheduling scheme comprising of genetic algorithm and simulated annealing techniques, both of which can efficiently explore the search space of all possible legal schedules to find a battery-efficient one. We demonstrate the effectiveness of our scheduling scheme over existing approaches on example task graphs and study the impact on battery life using a battery model. Our experimental results shows considerable improvement in battery life over existing approaches.
Citește tot Restrânge

Preț: 27086 lei

Preț vechi: 33857 lei
-20% Nou

Puncte Express: 406

Preț estimativ în valută:
5185 5390$ 4299£

Carte tipărită la comandă

Livrare economică 05-19 februarie 25

Preluare comenzi: 021 569.72.76

Specificații

ISBN-13: 9783848494521
ISBN-10: 3848494523
Pagini: 76
Dimensiuni: 152 x 229 x 5 mm
Greutate: 0.12 kg
Editura: LAP LAMBERT ACADEMIC PUBLISHING AG & CO KG
Colecția LAP Lambert Academic Publishing

Notă biografică

Srobona Mitra did her B.E. and M.Tech. in Comp. Sc. & Engg. from Jadavpur University, Kolkata in 2004 and Indian Institute of Technology Kharagpur, Kharagpur in 2006 respectively. She is now pursuing PhD in the Comp. Sc. & Engg. Dept. at IIT Kharagpur. Her research interests are Semi-Formal, Formal and Post-Silicon Verification of hardware designs.