Cantitate/Preț
Produs

Processor Architecture: From Dataflow to Superscalar and Beyond

Autor Jurij Silc, Borut Robic, Theo Ungerer
en Limba Engleză Paperback – 8 iun 1999
Today's microprocessors are the powerful descendants of the von Neumann 1 computer dating back to a memo of Burks, Goldstine, and von Neumann of 1946. The so-called von Neumann architecture is characterized by a se­ quential control flow resulting in a sequential instruction stream. A program counter addresses the next instruction if the preceding instruction is not a control instruction such as, e. g. , jump, branch, subprogram call or return. An instruction is coded in an instruction format of fixed or variable length, where the opcode is followed by one or more operands that can be data, addresses of data, or the address of an instruction in the case of a control instruction. The opcode defines the types of operands. Code and data are stored in a common storage that is linear, addressed in units of memory words (bytes, words, etc. ). The overwhelming design criterion of the von Neumann computer was the minimization of hardware and especially of storage. The most simple implementation of a von Neumann computer is characterized by a microar­ chitecture that defines a closely coupled control and arithmetic logic unit (ALU), a storage unit, and an I/O unit, all connected by a single connection unit. The instruction fetch by the control unit alternates with operand fetches and result stores for the AL U.
Citește tot Restrânge

Preț: 60738 lei

Preț vechi: 75922 lei
-20% Nou

Puncte Express: 911

Preț estimativ în valută:
11628 12104$ 9572£

Carte tipărită la comandă

Livrare economică 01-15 februarie 25

Preluare comenzi: 021 569.72.76

Specificații

ISBN-13: 9783540647980
ISBN-10: 3540647988
Pagini: 416
Ilustrații: XXII, 389 p. 14 illus.
Dimensiuni: 155 x 235 x 22 mm
Greutate: 1.28 kg
Ediția:Softcover reprint of the original 1st ed. 1999
Editura: Springer Berlin, Heidelberg
Colecția Springer
Locul publicării:Berlin, Heidelberg, Germany

Public țintă

Professional/practitioner

Cuprins

1. Basic Pipelining and Simple RISC Processors.- 1.1 The RISC Movement in Processor Architecture.- 1.2 Instruction Set Architecture.- 1.3 Examples of RISC ISAs.- 1.4 Basic Structure of a RISC Processor and Basic Cache MMU Organization.- 1.5 Basic Pipeline Stages.- 1.6 Pipeline Hazards and Solutions.- 1.7 RISC Processors.- 1.8 Lessons learned from RISC.- 2. Dataflow Processors.- 2.1 Dataflow Versus Control-Flow.- 2.2 Pure Dataflow.- 2.3 Augmenting Dataflow with Control-Flow.- 2.4 Lessons learned from Dataflow.- 3. CISC Processors.- 3.1 A Brief Look at CISC Processors.- 3.2 Out-of-Order Execution.- 3.3 Dynamic Scheduling.- 3.4 Some CISC Microprocessors.- 3.5 Conclusions.- 4. Multiple-Issue Processors.- 4.1 Overview of Multiple-Issue Processors.- 4.2 I-Cache Access and Instruction Fetch.- 4.3 Dynamic Branch Prediction and Control Speculation.- 4.4 Decode.- 4.5 Rename.- 4.6 Issue and Dispatch.- 4.7 Execution Stages.- 4.8 Finalizing Pipelined Execution.- 4.9 State-of-the-Art Superscalar Processors.- 4.10 VLIW and EPIC Processors.- 4.11 Conclusions on Multiple-Issue Processors.- 5. Future Processors to use Fine-Grain Parallelism.- 5.1 Trends and Principles in the Giga Chip Era.- 5.2 Advanced Superscalar Processors.- 5.3 Superspeculative Processors.- 5.4 Multiscalar Processors.- 5.5 Trace Processors.- 5.6 DataScalar Processors.- 5.7 Conclusions.- 6. Future Processors to use Coarse-Grain Parallelism.- 6.1 Utilization of more Coarse-Grain Parallelism.- 6.2 Chip Multiprocessors.- 6.3 Multithreaded Processors.- 6.4 Simultaneous Multithreading.- 6.5 Simultaneous Multithreading versus Chip Multiprocessor.- 6.6 Conclusions.- 7. Processor-in-Memory, Reconfigurable, and Asynchronous Processors.- 7.1 Processor-in-Memory.- 7.2 Reconfigurable Computing.- 7.3 Asynchronous Processors.- 7.4Conclusions.- Acronyms.- References.

Textul de pe ultima copertă

This monograph surveys architectural mechanisms and implementation techniques for exploiting fine-grained and coarse-grained parallelism within microprocessors. It starts with a review of past techniques, continues with a comprehensive account of state-of-the-art techniques used in microprocessors that covers both the concepts involved and implementations in sample processors, and ends with a thorough review of the research techniques that will lead to future microprocessors.

Caracteristici

The book describes all processor architecture technologies The authors also provide application-oriented methods for the development of new processors Includes supplementary material: sn.pub/extras