Resource Efficient LDPC Decoders: From Algorithms to Hardware Architectures
Autor Vikram Arkalgud Chandrasetty, Syed Mahfuzul Azizen Limba Engleză Paperback – 4 dec 2017
- Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation
- How to reduce computational complexity and power consumption using computer aided design techniques
- All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs
- Provides extensive treatment of LDPC decoding algorithms and hardware implementations
- Gives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware
- Companion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis
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Specificații
ISBN-13: 9780128112557
ISBN-10: 0128112557
Pagini: 190
Dimensiuni: 191 x 235 x 16 mm
Editura: ELSEVIER SCIENCE
ISBN-10: 0128112557
Pagini: 190
Dimensiuni: 191 x 235 x 16 mm
Editura: ELSEVIER SCIENCE
Public țintă
Electrical and electronic engineers engineers in academic and industry involved in the design of communication circuits, Research and development engineers in various government research organizations. Postgraduate research students (PhD and Masters) engaged in research in telecommunications and electronic engineering.Cuprins
1. Introduction2. Overview of LDPC codes3. Structure and flexibility of LDPC codes4. LDPC decoding algorithms5. LDPC decoder architectures6. Hardware implementation of LDPC decoder7. LDPC decoders in multimedia communication8. Prospective LDPC applications
AppendixA : Sample C-Programs and MATLAB models for LDPC code construction and simulationB : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architectureC : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture
AppendixA : Sample C-Programs and MATLAB models for LDPC code construction and simulationB : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architectureC : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture