RISC-V Microprocessor System-On-Chip Design
Autor David Harris, James Stine, Sarah Harris, Rose Thompsonen Limba Engleză Paperback – mai 2025
- Covers detailed design for all components of a nontrivial microprocessor
- Provides detailed explanations on the implementation of RISC-V microprocessors
- Uses open-source SystemVerilog code and test cases for the entire processor, including single-issue and superscalar cores, multicore, all extensions (including multiplication/division, floating point, and atomic memory operations), and common peripherals
- Enables users to build scripts to implement the processor on the open-source Skywater process
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Specificații
ISBN-13: 9780323994989
ISBN-10: 0323994989
Pagini: 600
Dimensiuni: 191 x 235 mm
Editura: ELSEVIER SCIENCE
ISBN-10: 0323994989
Pagini: 600
Dimensiuni: 191 x 235 mm
Editura: ELSEVIER SCIENCE
Cuprins
1. Introduction
Part 1: RISC-V Architecture
2. RISC-V Architecture
3. Assembly Language Programming
4. C Programming
Part 2: RISC-V Microarchitecture
5. Microarchitecture Overview
6. Survey of Microarchitectures
7. RISC-V Pipelined Microarchitecture
8. Privileged Operations
9. AHB Interface
10. Virtual Memory
11. Branch Prediction
12. RISC-V Superscalar Microarchitecture
13. RISC-V Threaded Microarchitecture
14. Extensions: Compressed Instructions
15. Extensions: Multiplication and Division
16. Extensions: Floating Point
17. Extensions: Atomic Operations
18. More Bus Interfaces
19. Peripherals
20. Multicore
21. SIMD
22. Vector
23. Bit Manipulation
24. Crypto
Part 3: Validation
25. Logic Verification
26. Performance Validation: Benchmarking
27. Linux Boot
Part 4: Implementation
28. FPGA Implementation
29. CMOS for Microarchitects
30. CMOS Implementation
31. Silicon Debug
Part 1: RISC-V Architecture
2. RISC-V Architecture
3. Assembly Language Programming
4. C Programming
Part 2: RISC-V Microarchitecture
5. Microarchitecture Overview
6. Survey of Microarchitectures
7. RISC-V Pipelined Microarchitecture
8. Privileged Operations
9. AHB Interface
10. Virtual Memory
11. Branch Prediction
12. RISC-V Superscalar Microarchitecture
13. RISC-V Threaded Microarchitecture
14. Extensions: Compressed Instructions
15. Extensions: Multiplication and Division
16. Extensions: Floating Point
17. Extensions: Atomic Operations
18. More Bus Interfaces
19. Peripherals
20. Multicore
21. SIMD
22. Vector
23. Bit Manipulation
24. Crypto
Part 3: Validation
25. Logic Verification
26. Performance Validation: Benchmarking
27. Linux Boot
Part 4: Implementation
28. FPGA Implementation
29. CMOS for Microarchitects
30. CMOS Implementation
31. Silicon Debug