It is getting increasingly difficult to verify processors and guarantee subsequent reliable operation. The complexity of processors is rapidly increasing with every new generation, leading to an increase in the number of design defects, ie. logical bugs in RTL. Simultaneously, with every new generation, process variations are making it tougher to ensure timing closure, leading to an increased susceptibility to timing faults. In this thesis we characterize and propose solutions to mitigate the effects of such congenital faults. We characterize RTL defects for 10 state of the art processors. Subsequently, we find common patterns and design an architecture to avoid such faults from manifesting. The process of testing for such defects is compounded by the fact that we have non-determinism in modern processors. We propose an architecture, CADRE, to remove most sources of non-determinism, and to allow of deterministic replay of faults. To redress the problem of process variation we propose a model of how parameter variation affects timing errors. We design a fuzzy logic based architecture that tries to maximize performance in the face of timing errors due to process variation.