The Designer's Guide to VHDL: Systems on Silicon, cartea 3
Autor Peter J. Ashendenen Limba Engleză Hardback – iul 2008
- First comprehensive book on VHDL to incorporate all new features of VHDL-2008, the latest release of the VHDL standard
- Helps readers get up to speed quickly with new features of the new standard
- Presents a structured guide to the modeling facilities offered by VHDL
- Shows how VHDL functions to help design digital systems
- Includes extensive case studies and source code used to develop testbenches and case study examples
- Helps readers gain maximum facility with VHDL for design of digital systems
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Specificații
ISBN-13: 9780120887859
ISBN-10: 0120887851
Pagini: 936
Ilustrații: Illustrated
Dimensiuni: 191 x 235 x 53 mm
Greutate: 2.05 kg
Ediția:3rd revised edition.
Editura: ELSEVIER SCIENCE
Seria Systems on Silicon
ISBN-10: 0120887851
Pagini: 936
Ilustrații: Illustrated
Dimensiuni: 191 x 235 x 53 mm
Greutate: 2.05 kg
Ediția:3rd revised edition.
Editura: ELSEVIER SCIENCE
Seria Systems on Silicon
Public țintă
Hardware Verification Engineers using VHDLCuprins
1. Fundamental Concepts
2. Scalar Data Types and Operations
3. Sequential Statements
4. Composite Data Types and Operations
5. Basic Modeling Constructs
6. Case Study: A Pipelined Complex Multiplier Accumulator
7. Subprograms
8. Packages and Use Clauses
9. Aliases
10. External Names in Testbenches
11. Properties and Assertion-Based Design
12. Resolved Signals
13. Generics
14. Components and Configurations
15. Generate Statements
16. Access Types and Abstract Data Types
17. Files and Input/Output
18. Case Study: Queuing Networks
19. Attributes and Groups
20. Design for Synthesis
21. Case Study: System Design using the Gumnut Core
22. Miscellaneous Topics
Appendix
A. Standard Packages
B. Related Standards
C. VHDL Syntax
D. Differences Among VHDL Versions
E. Answers to Exercises
2. Scalar Data Types and Operations
3. Sequential Statements
4. Composite Data Types and Operations
5. Basic Modeling Constructs
6. Case Study: A Pipelined Complex Multiplier Accumulator
7. Subprograms
8. Packages and Use Clauses
9. Aliases
10. External Names in Testbenches
11. Properties and Assertion-Based Design
12. Resolved Signals
13. Generics
14. Components and Configurations
15. Generate Statements
16. Access Types and Abstract Data Types
17. Files and Input/Output
18. Case Study: Queuing Networks
19. Attributes and Groups
20. Design for Synthesis
21. Case Study: System Design using the Gumnut Core
22. Miscellaneous Topics
Appendix
A. Standard Packages
B. Related Standards
C. VHDL Syntax
D. Differences Among VHDL Versions
E. Answers to Exercises