This thesis introduces the Integrated Emitter Turn-Off (IETO) Thyristor as a new high-power device. Known state-of-the-art research activities like the Dual GCT, the ETO thyristor and the ICT were presented and critically reviewed. A comparison with commercialized solutions identifies the pros and cons of each type of device family. Based on this analysis, the IETO structure is proposed, covering most benefits of each device class. In particular the combination of a MOS-assisted turn-off with a thyristor-based device allows a voltage-controlled MOS switching and the low on-state voltage of the thyristors.The following synthesis of an IETO device stands on a three-dimensional field of optimization spanned by electric, mechanical and thermal aspects. From an electric point of view, the lowest possible parasitic inductance and resistance within the commutation path are optimization criteria. The mechanical construction has to withstand the required contact pressure of multiple kilo Newtons. Finally, thermal borders limit the maximum average current of the device. FEM simulations covering these three aspects are performed for several design proposals. An IETO prototype is constructed and measurements on various test benches attest thermal, mechanical and electric performance. A local decoupling of the external driver stage and the presspack housing is presented by a cable connection. This separation enables a thermal and mechanical independence, which is advantageous in terms of vibrations and thermal cycles including increased reliability.The electric pulse performance of the prototype device is a factor of 3.1 above today's solutions. In single-pulse measurements, a current up to 1600 A was successfully turned off at 115°C with an active silicon area of 823 mm². One reason for this increased turn-off capability is the extremely low-inductive construction. Additional functionality of the IETO thyristor like over-current self-protection and defined short-circuit failure state are successfully verified.