Three-Dimensional Integrated Circuit Design
Autor Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedmanen Limba Engleză Paperback – 2 iul 2017
Expanded with new chapters and updates throughout based on the latest research in 3-D integration:
- Manufacturing techniques for 3-D ICs with TSVs
- Electrical modeling and closed-form expressions of through silicon vias
- Substrate noise coupling in heterogeneous 3-D ICs
- Design of 3-D ICs with inductive links
- Synchronization in 3-D ICs
- Variation effects on 3-D ICs
- Correlation of WID variations for intra-tier buffers and wires
- Offers practical guidance on designing 3-D heterogeneous systems
- Provides power delivery of 3-D ICs
- Demonstrates the use of 3-D ICs within heterogeneous systems that include a variety of materials, devices, processors, GPU-CPU integration, and more
- Provides experimental case studies in power delivery, synchronization, and thermal characterization
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Specificații
ISBN-13: 9780124105010
ISBN-10: 0124105017
Pagini: 768
Dimensiuni: 191 x 235 x 41 mm
Greutate: 1.47 kg
Ediția:2
Editura: ELSEVIER SCIENCE
ISBN-10: 0124105017
Pagini: 768
Dimensiuni: 191 x 235 x 41 mm
Greutate: 1.47 kg
Ediția:2
Editura: ELSEVIER SCIENCE
Public țintă
VSLI design engineers, processor designers, researchers and practitioners in circuit designCuprins
1. Introduction 2. Manufacturing of 3-D Packaged Systems 3. 3-D Integrated Circuit Fabrication Technologies 4. Electrical Modeling and Closed-Form Expressions of Through Silicon Vias 5. Substrate Noise Coupling in Heterogeneous 3-D ICs 6. Design of 3-D ICs with Inductive Links7. Interconnect Prediction Models 8. Cost Issues for 3-D Integrated Systems9. Physical Design Techniques for 3-D ICs 10. Timing Optimization for Two-Terminal Interconnects 11. Timing Optimization for Multi-Terminal Interconnects 12. Thermal Modeling and Analysis 13. Thermal Management Strategies for 3-D ICs 14. Case Study: Thermal Effects in a prototype 3-D IC 15. Three-Dimensional Networks-on-Chip 16. Synchronization in 3-D ICs 17. Case Study: Clock distribution in 3-D ICs 18. Variation Effects on 3-D ICs 19. Power Delivery and Distribution for 3-D ICs20. Case Study: Power Distribution Networks in 3-D ICs 21. Conclusions and Future Prospects
AppendixA: Enumeration of Gate Pairs in a 3-D ICB: Formal Proof of Optimum Single Via PlacementC: Proof of the Two-Terminal Via Placement HeuristicD: Proof of Condition for Via Placement of Multi-Terminal Nets GlossaryE: Correlation of WID Variations for Intra-Tier Buffers F: Extension of the Proposed Model to Include Variations of Wires
AppendixA: Enumeration of Gate Pairs in a 3-D ICB: Formal Proof of Optimum Single Via PlacementC: Proof of the Two-Terminal Via Placement HeuristicD: Proof of Condition for Via Placement of Multi-Terminal Nets GlossaryE: Correlation of WID Variations for Intra-Tier Buffers F: Extension of the Proposed Model to Include Variations of Wires