For some years ago the main statement among verification engineers was "Bugs in hardware cost money". Nowadays, the embedded software is playing an important role in the embedded systems industry and the statement can be updated to "Bugs in hardware and in software cost a lot of money". Embedded software is very powerful in embedded systems in order to implement important functionalities and functional innovations. The developing costs of embedded software are becoming huge and its amount in safety critical systems is increasing. Therefore, the verification of complex systems needs to consider the verification of both hardware and embedded software modules. The most commonly used approaches to verify embedded software are based on co- simulation or on co-debugging, which consume long verification time and additionally have coverage limitations. Formal verification assures complete coverage, but is limited to the size of the module that can be verified. This dissertation extends the conventional verification limitations with methodologies that are based on temporal properties and formal verification.