Cantitate/Preț
Produs
Total produse
Vezi coșul
Verilog Coding for Logic Synthesis de WF Lee

Verilog Coding for Logic Synthesis

Autor WF Lee
en Limba Engleză Hardback – 12 mai 2003
Provides a practical approach to Verilog design and problem solving. * Bulk of the book deals with practical design problems that design engineers solve on a daily basis. * Includes over 90 design examples. * There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification. * Book is suitable for use as a textbook in EE departments that have VLSI courses
Citește tot Restrânge

Preț: 94601 lei

Preț vechi: 103957 lei
-9% Nou

Puncte Express: 1419
Preț estimativ în valută:
18104€ • 18831$ • 14946£

Carte tipărită la comandă

Livrare economică 14-28 aprilie

 Adaugă în coș

Wish list
Gift list
Am citit!
Adaugă în listă
Preluare comenzi: 021 569.72.76

Specificații

ISBN-13: 9780471429760
ISBN-10: 0471429767
Pagini: 310
Dimensiuni: 166 x 240 x 23 mm
Greutate: 0.59 kg
Ediția:New.
Editura: Wiley
Locul publicării:Hoboken, United States

Public țintă

VLSI Design Engineers and Seniors and Graduate Students

Cuprins

Descriere

Verilog is a Hardware Description Language (HDL) used to design and document electronic systems. Verilog HDL allows designers to virtually design systems without expending time or resources on physical models. It is the most widely used HDL with a user community of more than 50,000 active designers.