60-GHz CMOS Phase-Locked Loops
Autor Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermunden Limba Engleză Paperback – 29 oct 2014
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Specificații
ISBN-13: 9789400790391
ISBN-10: 9400790392
Pagini: 208
Ilustrații: VIII, 197 p.
Dimensiuni: 155 x 235 x 11 mm
Greutate: 0.3 kg
Ediția:2010
Editura: SPRINGER NETHERLANDS
Colecția Springer
Locul publicării:Dordrecht, Netherlands
ISBN-10: 9400790392
Pagini: 208
Ilustrații: VIII, 197 p.
Dimensiuni: 155 x 235 x 11 mm
Greutate: 0.3 kg
Ediția:2010
Editura: SPRINGER NETHERLANDS
Colecția Springer
Locul publicării:Dordrecht, Netherlands
Public țintă
Professional/practitionerCuprins
Synthesizer System Architecture.- Layout and Measurements at mm-Wave Frequencies.- Design of High Frequency Components.- Design of Low Frequency Components.- Synthesizer Integration.- Conclusions.
Textul de pe ultima copertă
The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market.
60-GHz CMOS Phase-Locked Loops focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of individual components such as voltage controlled oscillators, injection locked frequency dividers and their combinations, are included. Furthermore, to satisfy a number of transceiver topologies simultaneously, flexibility is introduced in the PLL architecture by using new dual-mode ILFDs and switchable VCOs, while reusing the low frequency components at the same time.
60-GHz CMOS Phase-Locked Loops focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of individual components such as voltage controlled oscillators, injection locked frequency dividers and their combinations, are included. Furthermore, to satisfy a number of transceiver topologies simultaneously, flexibility is introduced in the PLL architecture by using new dual-mode ILFDs and switchable VCOs, while reusing the low frequency components at the same time.
Caracteristici
Offers a system level to circuit level design of 60-GHz PLLs Provides guidelines for millimeter-wave layout and measurement Covers both single-mode and dual-mode injection-locked frequency dividers Includes supplementary material: sn.pub/extras