A Pipelined Multi-Core Machine with Operating System Support: Hardware Implementation and Correctness Proof: Lecture Notes in Computer Science, cartea 9999
Autor Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paulen Limba Engleză Paperback – 10 mai 2020
This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
• MIPS instruction set architecture (ISA) for application and for system programming
• cache coherent memory system
• store buffers in front of the data caches
• interrupts and exceptions
• memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
• I/O-interrupt controller and a disk
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
• MIPS instruction set architecture (ISA) for application and for system programming
• cache coherent memory system
• store buffers in front of the data caches
• interrupts and exceptions
• memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
• I/O-interrupt controller and a disk
Din seria Lecture Notes in Computer Science
- 20%
Preț: 1043.63 lei - 20%
Preț: 334.61 lei - 20%
Preț: 336.22 lei - 20%
Preț: 445.69 lei - 20%
Preț: 238.01 lei - 20%
Preț: 334.61 lei - 20%
Preț: 438.69 lei -
Preț: 442.03 lei - 20%
Preț: 337.87 lei - 20%
Preț: 148.66 lei - 20%
Preț: 310.26 lei - 20%
Preț: 256.27 lei - 20%
Preț: 634.41 lei - 17%
Preț: 427.22 lei - 20%
Preț: 643.99 lei - 20%
Preț: 307.71 lei - 20%
Preț: 1057.10 lei - 20%
Preț: 581.55 lei -
Preț: 374.84 lei - 20%
Preț: 331.36 lei - 15%
Preț: 431.22 lei - 20%
Preț: 607.39 lei - 20%
Preț: 538.29 lei -
Preț: 389.48 lei - 20%
Preț: 326.98 lei - 20%
Preț: 1390.89 lei - 20%
Preț: 1007.16 lei - 20%
Preț: 569.54 lei - 20%
Preț: 575.48 lei - 20%
Preț: 573.59 lei - 20%
Preț: 750.35 lei - 15%
Preț: 570.71 lei - 17%
Preț: 360.19 lei - 20%
Preț: 504.57 lei - 20%
Preț: 172.69 lei - 20%
Preț: 369.12 lei - 20%
Preț: 347.59 lei - 20%
Preț: 576.02 lei -
Preț: 404.00 lei - 20%
Preț: 586.43 lei - 20%
Preț: 750.35 lei - 20%
Preț: 812.01 lei - 20%
Preț: 649.49 lei - 20%
Preț: 344.34 lei - 20%
Preț: 309.90 lei - 20%
Preț: 122.89 lei
Preț: 343.69 lei
Preț vechi: 429.61 lei
-20% Nou
Puncte Express: 516
Preț estimativ în valută:
65.77€ • 68.52$ • 54.69£
65.77€ • 68.52$ • 54.69£
Carte tipărită la comandă
Livrare economică 11-25 februarie 25
Preluare comenzi: 021 569.72.76
Specificații
ISBN-13: 9783030432423
ISBN-10: 3030432424
Pagini: 628
Ilustrații: XV, 628 p. 1 illus.
Dimensiuni: 155 x 235 mm
Greutate: 0.89 kg
Ediția:1st ed. 2020
Editura: Springer International Publishing
Colecția Springer
Seriile Lecture Notes in Computer Science, Theoretical Computer Science and General Issues
Locul publicării:Cham, Switzerland
ISBN-10: 3030432424
Pagini: 628
Ilustrații: XV, 628 p. 1 illus.
Dimensiuni: 155 x 235 mm
Greutate: 0.89 kg
Ediția:1st ed. 2020
Editura: Springer International Publishing
Colecția Springer
Seriile Lecture Notes in Computer Science, Theoretical Computer Science and General Issues
Locul publicării:Cham, Switzerland
Cuprins
Introductory material.- on hierarchical hardware design.- hardware library.- basic processor design.- pipelining.- cache memory systems.- interrupt mechanism.- self modification, instruction buffer and nondeterministic ISA.- memory management units.- store buffers.- multi-core processors.- advanced programmable interrupt controllers (APICs).- adding a disk.- I/O apic.
Textul de pe ultima copertă
This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
• MIPS instruction set architecture (ISA) for application and for system programming
• cache coherent memory system
• store buffers in front of the data caches • interrupts and exceptions
• memory management units (MMUs)
• pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
• I/O-interrupt controller and a disk
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
• MIPS instruction set architecture (ISA) for application and for system programming
• cache coherent memory system
• store buffers in front of the data caches • interrupts and exceptions
• memory management units (MMUs)
• pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
• I/O-interrupt controller and a disk
Caracteristici
Future development based on LNCS 9000 published in 2014 Monograph by well-known experts in the field Presents construction and correctness proof of the MIPS instruction set architecture