Architecture Design and Validation Methods
Editat de Egon Börgeren Limba Engleză Paperback – 23 oct 2012
Toate formatele și edițiile | Preț | Express |
---|---|---|
Paperback (1) | 336.21 lei 6-8 săpt. | |
Springer Berlin, Heidelberg – 23 oct 2012 | 336.21 lei 6-8 săpt. | |
Hardback (1) | 338.49 lei 6-8 săpt. | |
Springer Berlin, Heidelberg – 6 mar 2000 | 338.49 lei 6-8 săpt. |
Preț: 336.21 lei
Preț vechi: 420.26 lei
-20% Nou
Puncte Express: 504
Preț estimativ în valută:
64.35€ • 66.93$ • 53.93£
64.35€ • 66.93$ • 53.93£
Carte tipărită la comandă
Livrare economică 13-27 martie
Preluare comenzi: 021 569.72.76
Specificații
ISBN-13: 9783642629761
ISBN-10: 3642629768
Pagini: 372
Ilustrații: X, 357 p.
Dimensiuni: 155 x 235 x 20 mm
Greutate: 0.52 kg
Ediția:Softcover reprint of the original 1st ed. 2000
Editura: Springer Berlin, Heidelberg
Colecția Springer
Locul publicării:Berlin, Heidelberg, Germany
ISBN-10: 3642629768
Pagini: 372
Ilustrații: X, 357 p.
Dimensiuni: 155 x 235 x 20 mm
Greutate: 0.52 kg
Ediția:Softcover reprint of the original 1st ed. 2000
Editura: Springer Berlin, Heidelberg
Colecția Springer
Locul publicării:Berlin, Heidelberg, Germany
Public țintă
ResearchCuprins
Modeling and Synthesis of Behavior, Control and Data Flow.- 1 Introduction.- 2 Behavioral Synthesis.- 3 High-Level Control.- 4 Data Flow.- 5 Conclusion.- References.- Cell-based Logic Optimization.- 1 Introduction.- 2 Problem Formulation and Analysis.- 3 Algorithms for Library Binding.- 4 Boolean Matching.- 5 Generalized Matching.- 6 Conclusion.- References.- A Design Flow for Performance Planning: New Paradigms for Iteration Free Synthesis.- 1 Introduction.- 2 Flow Components.- 3 Layout Synthesis.- 4 Placement Versus Floorplan Design.- 5 Global Wires.- 6 Wire Planning.- 7 Gate Sizing.- 8 Conclusions.- References.- Test and Testable Design.- 1 Introduction.- 2 Defect Analysis and Fault Modeling.- 3 External Testing.- 4 Self-Testable Systems-On-Chip.- References.- Machine Assisted Verification.- 1 Introduction.- 2 Logic Verification.- 3 Bit-Vector and Word-Level Verification.- 4 Verification by Fixed-Point Calculations.- 5 Verification Techniques for Bounded State Sequences.- 6 Formally Correct Construction of Pipelined Systems.- References.- Models of Computation for System Design.- 1 Introduction.- 2 MOCs: Basic Concepts and the Tagged Signal Model.- 3 Common Models of Computation.- 4 Codesign Finite State Machines.- 5 Conclusions.- References.- Modular Design for the Java Virtual Machine Architecture.- 1 Introduction.- 2 The Trustful Virtual Machine.- 3 The Defensive Virtual Machine.- 4 The Diligent Virtual Machine.- 5 The Dynamic Virtual Machine.- 6 Related and Future Work.- 7 The JVM Abstract State Machine.
Caracteristici
Comprehensive state-of-the-art survey of design and validation of computer architectures Systematic coverage providing a clear vision of the problems and advanced techniques for their solution Seven chapters by eminent researchers presuppose only basic knowledge and lead to the forefront of research Includes supplementary material: sn.pub/extras