Architecture of Computing Systems -- ARCS 2016: 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings: Lecture Notes in Computer Science, cartea 9637
Editat de Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teichen Limba Engleză Paperback – 25 mar 2016
The 29 full papers presented in this volume werecarefully reviewed and selected from 87 submissions. They were organized intopical sections named: configurable and in-memory accelerators;network-on-chip and secure computing architectures; cache architectures andprotocols; mapping of applications on heterogeneous architectures and real-timetasks on multiprocessors; all about time: timing, tracing, and performancemodeling; approximate and energy-efficient computing; allocation: from memoriesto FPGA hardware modules; organic computing systems; and reliability aspects inNoCs, caches, and GPUs.
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Specificații
ISBN-13: 9783319306940
ISBN-10: 3319306944
Pagini: 402
Ilustrații: XX, 402 p. 164 illus.
Dimensiuni: 155 x 235 x 22 mm
Greutate: 0.59 kg
Ediția:1st ed. 2016
Editura: Springer International Publishing
Colecția Springer
Seriile Lecture Notes in Computer Science, Theoretical Computer Science and General Issues
Locul publicării:Cham, Switzerland
ISBN-10: 3319306944
Pagini: 402
Ilustrații: XX, 402 p. 164 illus.
Dimensiuni: 155 x 235 x 22 mm
Greutate: 0.59 kg
Ediția:1st ed. 2016
Editura: Springer International Publishing
Colecția Springer
Seriile Lecture Notes in Computer Science, Theoretical Computer Science and General Issues
Locul publicării:Cham, Switzerland
Cuprins
Configurable and In-Memory Accelerators.- TowardsMulticore Performance with Configurable Computing Units.- Design and Evaluationof a Processing-in-Memory Architecture for the Smart Memory Cube.- Network-on-Chipand Secure Computing Architectures.- CASCADE: Congestion Aware Switchable CycleAdaptive Detection Router.- An Alternating Transmission Scheme for DetectionRouting based Network-on-Chips.- Exzess: Hardware-based RAM Encryption againstPhysical Memory Disclosure.- Hardware-Assisted Context Management forAccelerator Virtualization: A Case Study with RSA.- Cache Architectures andProtocols Adaptive Cache Structures.- Optimization of a Linked Cache CoherenceProtocol for Scalable Manycore Coherence.- Mapping of Applications onHeterogeneous.- Architectures and Real-Time Tasks on Multiprocessors Genericalgorithmic scheme for 2D stencil applications on heterogeneous hybrid machines.-GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive LoadBalancing.- Task Variants with Different Scratchpad Memory Consumption inMulti-Task Environments.- Feedback-Based Admission Control for Hard Real-TimeTask Allocation under Dynamic Workload on Many-core Systems.- All About Time:Timing, Tracing, and Performance Modeling Data Age Diminution in the LogicalExecution Time Model.- Accurate Sample Time Reconstruction for Sensor DataSynchronization.- DiaSys: On-Chip Trace Analysis for Multi-ProcessorSystem-on-Chip.- Analysis of Intel's Haswell Microarchitecture Using The ECMModel and Microbenchmarks.- Measurement-Based Probabilistic Timing Analysis forGraphics Processor Units.- Approximate and Energy-Efficient Computing.- ReducingEnergy Consumption of Data Transfers using Runtime Data Type Conversion.-Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector.-Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode DecisionProcess Using Actor-based Modeling.- Low-Cost Hardware Infrastructure forRuntime Thread Level Energy Accounting.- Allocation: From Memories to FPGAHardware Modules Reducing NoC and Memory Contention for Manycores.- An EfficientData Structure for Dynamic Two-Dimensional Reconfiguration.- Organic ComputingSystems Runtime Clustering of Similarly Behaving Agents in Open Organic ComputingSystems.- Comparison of Dependency Measures for the Detection of Mutual Influencesin Organic Computing Systems.- Augmenting the Algorithmic Structure of XCS byMeans of Interpolation.- Reliability Aspects in NoCs, Caches, and GPUs Estimationof End-to-end Packet Error Rates for NoC Multicasts.- Protecting Code Regionson Asymmetrically Reliable Caches.- A New Simulation-based Fault InjectionApproach for the Evaluation of Transient Errors in GPGPUs.
Caracteristici
Includes supplementary material: sn.pub/extras