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Automated Analysis of Virtual Prototypes at the Electronic System Level: Design Understanding and Applications

Autor Mehran Goli, Rolf Drechsler
en Limba Engleză Paperback – 5 mai 2021
This book describes a set of SystemC‐based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration.  Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL). The methodologies discussed enable readers to tackle easily key tasks and applications in the design process.
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Specificații

ISBN-13: 9783030442842
ISBN-10: 3030442845
Pagini: 166
Ilustrații: XXI, 166 p. 53 illus.
Dimensiuni: 155 x 235 mm
Greutate: 0.27 kg
Ediția:1st ed. 2020
Editura: Springer International Publishing
Colecția Springer
Locul publicării:Cham, Switzerland

Cuprins

Chapter 1. Introduction.- Chapter 2. Background.- Chapter 3. Design Understanding Methodology.- Chapter 4. Application I: Verification.- Chapter 5. Application II: Security Validation.- Chapter 6. Application III: Design Space Exploration.- Chapter 7. Conclusion.


Notă biografică

Mehran Goli is a Researcher at the German Research Center for Artificial Intelligence (DFKI) since 2018. He received the B.Sc. degree in computer engineering from the University of Shahid Beheshti, Tehran, Iran, in 2012,  M.Sc. degree in computer engineering from the University of Tehran, Tehran, Iran, in 2015, and Dr.-Ing. degree in computer science from  the University of Bremen, Bremen, Germany, in 2019. His current research interests include system level design, verification, and security validation.
Rolf Drechsler received the Diploma and Dr. Phil. Nat. degrees in computer science from J.W. Goethe University Frankfurt am Main, Frankfurt am Main, Germany, in 1992 and 1995, respectively. He was with the Institute of Computer Science, Albert‐Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and with the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001. Since October 2001, he has been with the University ofBremen, Bremen, Germany, where he is currently a Full Professor and the Head of the Group for Computer Architecture, Institute of Computer Science. In 2011, he additionally became the Director of the Cyber Physical Systems group at the German Research Center for Artificial Intelligence (DFKI) in Bremen. His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design. He is an IEEE Fellow.


Textul de pe ultima copertă

This book describes a set of SystemC‐based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration.  Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL). The methodologies discussed enable readers to tackle easily key tasks and applications in the design process.
  • Provides an extensive introduction to the field of SystemC‐based virtual prototype (VP) analysis at the electronic system level;
  • Describes a design understanding methodology from both debugger-based and compiler‐based perspectives;
  • Illustrates a semi‐formal verification approach to check the validity of a given VP against its specification, user‐defined rules and protocol;
  • Discusses a security validation approach to validate the run‐time behavior of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity);
  • Describes a design space exploration approach for SystemC-based VPs to guide designers to know under which error limits, different portions of a given VP can be approximated at different granularity levels.

Caracteristici

Provides an extensive introduction to the field of SystemC-based virtual prototype (VP) analysis at the electronic system level Describes a design understanding methodology from both debugger-based and compiler-based perspectives Illustrates a semi-formal verification approach to check the validity of a given VP against its specification, user-defined rules and protocol Discusses a security validation approach to validate the run-time behavior of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity) Describes a design space exploration approach for SystemC-based VPs to guide designers to know under which error limits, different portions of a given VP can be approximated at different granularity levels