Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design
Autor David Chinnery, Kurt Keutzeren Limba Engleză Paperback – 29 oct 2010
Important topics include:
- Microarchitectural techniques to reduce energy per operation
- Power reduction with timing slack from pipelining
- Analysis of the benefits of using multiple supply and threshold voltages
- Placement techniques for multiple supply voltages
- Verification for multiple voltage domains
- Improved algorithms for gate sizing, and assignment of supply and threshold voltages
- Power gating design automation to reduce leakage
- Relationships among tatistical timing, power analysis, and parametric yield optimization
Design examples illustrate that these techniques can improve energy efficiency by two to three times.
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Springer Us – 6 sep 2007 | 935.41 lei 6-8 săpt. |
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Specificații
ISBN-13: 9781441938336
ISBN-10: 1441938338
Pagini: 396
Ilustrații: XII, 388 p. 138 illus.
Dimensiuni: 155 x 235 x 21 mm
Greutate: 0.55 kg
Ediția:Softcover reprint of hardcover 1st ed. 2007
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
ISBN-10: 1441938338
Pagini: 396
Ilustrații: XII, 388 p. 138 illus.
Dimensiuni: 155 x 235 x 21 mm
Greutate: 0.55 kg
Ediția:Softcover reprint of hardcover 1st ed. 2007
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
Overview of the Factors Affecting the Power Consumption.- Pipelining to Reduce the Power.- Voltage Scaling.- Methodology to Optimize Energy of Computation for SOCs.- Linear Programming for Gate Sizing.- Linear Programming for Multi-Vth and Multi-Vdd Assignment.- Power Optimization using Multiple Supply Voltages.- Placement for Power Optimization.- Power Gating Design Automation.- Verification For Multiple Supply Voltage Designs.- Winning the Power Struggle in an Uncertain Era.- Pushing ASIC Performance in a Power Envelope.- Low Power ARM 1136JF-S Design.
Textul de pe ultima copertă
This book carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology.
Important topics include:
- Microarchitectural techniques to reduce energy per operation
- Power reduction with timing slack from pipelining
- Analysis of the benefits of using multiple supply and threshold voltages
- Placement techniques for multiple supply voltages
- Verification for multiple voltage domains
- Improved algorithms for gate sizing, and assignment of supply and threshold voltages
- Power gating design automation to reduce leakage
- Relationships among statistical timing, power analysis, and parametric yield optimization
Design examples illustrate that these techniques can improve energy efficiency by two to three times.
Important topics include:
- Microarchitectural techniques to reduce energy per operation
- Power reduction with timing slack from pipelining
- Analysis of the benefits of using multiple supply and threshold voltages
- Placement techniques for multiple supply voltages
- Verification for multiple voltage domains
- Improved algorithms for gate sizing, and assignment of supply and threshold voltages
- Power gating design automation to reduce leakage
- Relationships among statistical timing, power analysis, and parametric yield optimization
Design examples illustrate that these techniques can improve energy efficiency by two to three times.
Caracteristici
Will cover how to use low power design in an automated design flow, and examine the design time and performance trade-offs Includes the latest tools and techniques for low power design applied in an ASIC design flow Focuses on low power in an automated design methodology; a much neglected area Includes supplementary material: sn.pub/extras