Cantitate/Preț
Produs
Total produse
Vezi coșul
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits de Sung Kyu Lim

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

Autor Sung Kyu Lim
en Limba Engleză Paperback – 16 dec 2014
This book provides readers with a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It describes numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs developed with the tools covered in the book. This book will also feature sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs. Full details of the related algorithms will be provided so that the readers will be able not only to grasp the core mechanics of the physical design tools, but also to be able to reproduce and improve upon the results themselves. This book will also offer various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process.
Citește tot Restrânge

Toate formatele și edițiile

Toate formatele și edițiile Preț Express
Paperback (1) 69682 lei  6-8 săpt.
  Springer – 16 dec 2014 69682 lei  6-8 săpt.
Hardback (1) 94130 lei  6-8 săpt.
  Springer – 25 noi 2012 94130 lei  6-8 săpt.

Preț: 69682 lei

Preț vechi: 81979 lei
-15% Nou

Puncte Express: 1045
Preț estimativ în valută:
13334€ • 14028$ • 11040£

Carte tipărită la comandă

Livrare economică 14-28 ianuarie 25

 Adaugă în coș

Wish list
Gift list
Am citit!
Adaugă în listă
Preluare comenzi: 021 569.72.76

Specificații

ISBN-13: 9781489986962
ISBN-10: 1489986960
Pagini: 588
Ilustrații: XXVIII, 560 p.
Dimensiuni: 155 x 235 x 31 mm
Greutate: 0.82 kg
Ediția:2013
Editura: Springer
Colecția Springer
Locul publicării:New York, NY, United States

Public țintă

Research

Cuprins

Regular vs Irregular TSV Placementfor 3D IC.- Steiner Routingfor 3D IC.- Buffer Insertion for 3D IC.-  Low Power Clock Routing for 3D IC.- Power Delivery Network Design for 3D IC.- 3D Clock Routing for Pre-bond Testability.- TSV-to-TSV Coupling Analysis and Optimization.- TSV Current Crowding and Power Integrity.- Modeling of Atomic Concentration at the Wire-to-TSV Interface.- Multi-Objective Archetectural Floorplanning for 3D IC.- Thermal-aware Gate-level Placement for 3D IC.- 3D IC Cooling with Micro-Fluidic Channels.- Mechanical Reliability Analysis and Optimization for 3D IC.- Impact of Mechanical Stress on Timing Variation for 3D IC.- Chip/Package Co-Analysis of Mechanical Stress for 3D IC.- 3D Chip/Packaging Co-Analysis of Stress-Induced Timing Variations.- TSV Interfracial Crack Analysis and Optimization.- Ultra High Logic Designs Using Monolithic 3D Integration.- Impact of TSV Scaling on 3D IC Design Quality.- 3D-MAPS: 3DMassively Parallel Processor with Stacked Memory.

Textul de pe ultima copertă

This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits.  It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs.  Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process.
  • Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability.
  • Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the electro-migration failure mechanisms in TSVs.
  • Covers design-for-thermal-reliability in 3D ICs, including thermal-aware architectural floorplanning, gate-level placement techniques to alleviate thermal problems, and co-design and co-analysis of thermal, power delivery, and performance.
  • Includes issues affecting design-for-mechanical-reliability in 3D ICs, such as the co-efficient of thermal expansion (CTE) mismatch between TSV and silicon substrate, device mobility and full-chip timing variations, and the impact of package elements.

Caracteristici

Describes numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs Features sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs Provides full details of all key algorithms, for maximum understanding and utility Includes design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process Includes supplementary material: sn.pub/extras