Design of Systems on a Chip: Design and Test
Editat de Ricardo Reis, Marcelo Soares Lubaszewski, Jochen A.G. Jessen Limba Engleză Hardback – 3 oct 2006
Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault toleranttechniques for programmable logic applications.
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Specificații
ISBN-13: 9780387324999
ISBN-10: 0387324992
Pagini: 234
Ilustrații: X, 234 p.
Dimensiuni: 156 x 234 x 14 mm
Greutate: 0.52 kg
Ediția:2007
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
ISBN-10: 0387324992
Pagini: 234
Ilustrații: X, 234 p.
Dimensiuni: 156 x 234 x 14 mm
Greutate: 0.52 kg
Ediția:2007
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
Design of Systems on a Chip.- Microsystems Technology and Applications.- Core Architectures for Digital Media and the Associated Compilation Techniques.- Past, Present and Future of Microprocessors.- Physical Design Automation.- Behavioral Synthesis: an Overview.- Hardware/Software co-design.- Test and Design-for-Test: from Circuits to Integrated Systems.- Synthesis of FPGAs and Testable ASICs.- Testable Design and Testing of Microsystems.- Embedded Core-based System-on-Chip Test Strategies.
Notă biografică
Ricardo Reis is a former president of the Brazilian Computer Society and former vice-president of the Brazilian Microelectronics Society. He is now trustee of both societies. He is a trustee and former vice-president of the International Federation for Information Processing, IFIP. He received the Silver Core Award from IFIP. He is member of IFIP TC10 and WG 10.5. He is the Editor-in-Chief of the Journal of Integrated Circuits and Systems, JICS. Ricardo is also Member of the Editorial Board Latin America liaison of the IEEE D&T as Latin America liaison. He contributed to the organizing and program committees of several a large number of international conferences (like VLSI-SoC, ISVLSI, ISSS+CODES, PATMOS, RAW, LATW, SBCCI, IFIP World Congress, …) and he is a founder of the SBCCI conference series (Symposium on Integrated Circuits and Systems Design). He is also Editor of several books.
Caracteristici
A practical and academic overview of Systems-on-Chip Design and test aspects are high lighted