Cantitate/Preț
Produs
Total produse
Vezi coșul
Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs de Jesús Ruiz-Amaya

Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs

Autor Jesús Ruiz-Amaya, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez
en Limba Engleză Paperback – 26 noi 2014
This book presents models and procedures to design pipeline analog-to-digital converters, compensating for device inaccuracies, so that high-performance specs can be met within short design cycles. These models are capable of capturing and predicting the behavior of pipeline data converters within less than half-a-bit deviation, versus transistor-level simulations. As a result, far fewer model iterations are required across the design cycle. Models described in this book accurately predict transient behaviors, which are key to the performance of discrete-time systems and hence to the performance of pipeline data converters.
Citește tot Restrânge

Toate formatele și edițiile

Toate formatele și edițiile Preț Express
Paperback (1) 70860 lei  6-8 săpt.
  Springer – 26 noi 2014 70860 lei  6-8 săpt.
Hardback (1) 63001 lei  6-8 săpt.
  Springer – 15 iul 2011 63001 lei  6-8 săpt.

Preț: 70860 lei

Preț vechi: 86415 lei
-18% Nou

Puncte Express: 1063
Preț estimativ în valută:
13563€ • 14228$ • 11251£

Carte tipărită la comandă

Livrare economică 29 ianuarie-12 februarie 25

 Adaugă în coș

Wish list
Gift list
Am citit!
Adaugă în listă
Preluare comenzi: 021 569.72.76

Specificații

ISBN-13: 9781489993182
ISBN-10: 1489993185
Pagini: 224
Ilustrații: XIII, 209 p.
Dimensiuni: 155 x 235 x 12 mm
Greutate: 0.32 kg
Ediția:2011
Editura: Springer
Colecția Springer
Locul publicării:New York, NY, United States

Public țintă

Research

Cuprins

Pipeline ADC Overview.- Design Methodologies for Pipeline ADCs.- Pipeline ADC Electrical-level Synthesis Tool.- Behavioural Modeling of Pipeline ADCs.- Case Study: Design of a 10BIT@60MS Pipeline ADC.- Experimental Results and State of the Art.- Conclusions and Future Lines of Research.

Textul de pe ultima copertă

This book presents models and procedures to design pipeline analog-to-digital converters, compensating for device inaccuracies, so that high-performance specs can be met within short design cycles. These models are capable of capturing and predicting the behavior of pipeline data converters within less than half-a-bit deviation, versus transistor-level simulations.  As a result, far fewer model iterations are required across the design cycle. Models described in this book accurately predict transient behaviors, which are key to the performance of discrete-time systems and hence to the performance of pipeline data converters.
  •  Describes efficient procedures for heirarchical top-down design of pipeline converters;

  •  Presents new methodologies to reduce bottom-up iterations, through inherent embedding of transistor-level parameters, such as parasitic capacitances, transconductances, and saturation currents;
     
  • Provides mathematical details of behavioral models, includes descriptions of the synthesis methods and associated tools and illustrates models through case studies supported by silicon prototypes.
 
 

 


 

Caracteristici

Describes efficient procedures for hierarchical top-down design of pipeline converters Presents new methodologies to reduce bottom-up iterations, through inherent embedding of transistor-level parameters, such as parasitic capacitances, transconductances, and saturation currents Provides mathematical details of behavioral models, includes descriptions of the synthesis methods and associated tools and illustrates models through case studies supported by silicon prototypes Includes supplementary material: sn.pub/extras