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Digital Logic Design Using Verilog: Coding and RTL Synthesis de Vaibbhav Taraate

Digital Logic Design Using Verilog: Coding and RTL Synthesis

Autor Vaibbhav Taraate
en Limba Engleză Hardback – noi 2021
This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists. 
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Specificații

ISBN-13: 9789811631986
ISBN-10: 9811631980
Pagini: 604
Ilustrații: XXV, 604 p. 652 illus., 529 illus. in color.
Dimensiuni: 155 x 235 mm
Greutate: 1.05 kg
Ediția:2nd ed. 2022
Editura: Springer Nature Singapore
Colecția Springer
Locul publicării:Singapore, Singapore

Cuprins

Introduction.- Combinational Logic Design (Part I).- Combinational Logic Design (Part II).- Combinational Design Guidelines.- Sequential Logic Design.- Sequential Design Guidelines.- Complex Designs using Verilog RTL.- Finite State Machines.- Simulation Concepts and PLD Based Designs.- RTL Synthesis.- Static Timing Analysis (STA).- Constraining Design.- Multiple Clock Domain Designs.- Low Power Design.- RTL Design for SOCs.

Notă biografică

Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

Textul de pe ultima copertă

This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists. 

Caracteristici

Consists of practical scenarios and issues that are helpful to students and professionals Covers case studies using Verilog and use of Verilog to implement the ASIC and FPGA based designs Provides over 200 practical examples Request lecturer material: sn.pub/lecturer-material

Recenzii

“This book presents digital logic design using the hardware description language known as Verilog. … The book will help readers learn digital logic design and become familiar enough with it to work with it further in the future. It is mainly aimed as a textbook for undergraduate students to implement digital logic design in a lab. The book discusses logic design in a well-structured way covering basic to intermediate concepts.” (J. Arul, Computing Reviews, April, 2017)