Cantitate/Preț
Produs
Total produse
Vezi coșul
Instruction Level Parallelism de Alex Aiken

Instruction Level Parallelism

Autor Alex Aiken, Utpal Banerjee, Arun Kejariwal, Alexandru Nicolau
en Limba Engleză Hardback – 30 noi 2016
This book precisely formulates and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques. With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in the optimization of performanceas well as area and power minimization of computer designs.


Citește tot Restrânge

Toate formatele și edițiile

Toate formatele și edițiile Preț Express
Paperback (1) 50176 lei  6-8 săpt.
  Springer Us – 29 iun 2018 50176 lei  6-8 săpt.
Hardback (1) 73056 lei  6-8 săpt.
  Springer Us – 30 noi 2016 73056 lei  6-8 săpt.

Preț: 73056 lei

Preț vechi: 91320 lei
-20% Nou

Puncte Express: 1096
Preț estimativ în valută:
13990€ • 15140$ • 11663£

Carte tipărită la comandă

Livrare economică 09-23 decembrie

 Adaugă în coș

Wish list
Gift list
Am citit!
Adaugă în listă
Preluare comenzi: 021 569.72.76

Specificații

ISBN-13: 9781489977953
ISBN-10: 1489977953
Pagini: 240
Ilustrații: XXI, 255 p. 78 illus., 30 illus. in color.
Dimensiuni: 155 x 235 x 22 mm
Greutate: 5.44 kg
Ediția:1st ed. 2016
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States

Cuprins

Introduction.- Overview of ILP Architectures.- Scheduling Basic Blocks.- Trace Scheduling.- Percolation Scheduling.- Modulo Scheduling.- Software Pipelining by Kernal Recognition.- Epilogue.

Notă biografică

Alex Aiken is the Alcatel-Lucent Professor and the current chair of the Computer Science Department at Stanford. His research interests include most areas of programming languages and compilers and particularly automated methods of analysis for both high performance and high reliability.


Utpal Banerjee has a PhD in mathematics from Carnegie-Mellon University and a PhD in computer science from the University of Illinois at Urbana-Champaign. He has taught at the University of Cincinnati, Arizona State University and the University of Illinois. Dr. Banerjee has served as a research staff member at Honeywell, Fairchild, Control Data and Intel corporations. His current affiliation is with the Department of Computer Science, University of California at Irvine. He has published a number of papers and books on restructuring compilers, including encyclopedia articles and a series of books on loop transformations. He is a fellow of the IEEE and a fellow of the ACM. 


Arun Kejariwal is a Statistical Learning Principal at Machine Zone. He co-founded MZ Research and currently manages a team of research scientists. He is leading the research and development of novel algorithms for fraud detection, anomaly detection in security and operational data. Prior to joining Machine Zone, he was a lead in the Data Fidelity Team at Twitter and open sourced standalone R packages for anomaly detection and breakout detection. He received Ph.D. in Computer Science from UC Irvine and is a Senior Member of IEEE and ACM.


Alexandru Nicolau’s research is in the areas of Parallel Processing/ILP, and Embedded Systems/Design Automation. His interests focus on Computer Performance/power tradeoffs, parallelizing compilers, GPUs. His current work involves collaborations both within and outside UCI, most recently with researchers at Stanford, University of Michigan, UCLA, UCSD as part of a flagship NSF Expedition project, and a separate grant with UIUC. He authored over 300 peer-reviewed papers and several books. He is the Editor-in-Chief of the International Journal of Parallel Processing, and an IEEE Fellow.

Textul de pe ultima copertă

Since its introduction decades ago, Instruction Level Parallelism (ILP) has gradually become ubiquitous and is now featured in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors.  Because these architectures could not exist or (in the case of superscalar machines) cannot achieve their full potential without specific sophisticated compilation techniques to exploit ILP, the development of architectures that support ILP has proceeded hand-in-hand with the development of sophisticated compiler technology, such as Trace Scheduling and Software Pipelining. While essential for achieving the full potential of ILP, in both performance as well as power consumption management, these techniques are still not widely known, in part because of their intricacy and in part because the only widely available references for ILP techniques are the primary resources, with the brevity of introduction common to conference proceedings.

This book precisely formulates, and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques.  With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in theoptimization of performance as well as area and power minimization of computer designs.




Caracteristici

Presents an unprecedented text, uniquely dedicated to Instruction Level Parallelism (ILP) Provides a detailed examination of ILP architectures Offers practical descriptions of key scheduling algorithms for extracting ILP at compile time Illustrates how algorithms can be applied to streaming computations and compilation for Graphics Processing Units (GPUs) Equips readers with a resourceful and comprehensive bibliography that spans over five decades Includes supplementary material: sn.pub/extras