Network-on-Chip Architectures: A Holistic Design Exploration: Lecture Notes in Electrical Engineering, cartea 45
Autor Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Dasen Limba Engleză Paperback – 14 mar 2012
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Specificații
ISBN-13: 9789400730496
ISBN-10: 9400730497
Pagini: 248
Ilustrații: XXII, 223 p.
Dimensiuni: 155 x 235 x 13 mm
Greutate: 0.35 kg
Ediția:2010
Editura: SPRINGER NETHERLANDS
Colecția Springer
Seria Lecture Notes in Electrical Engineering
Locul publicării:Dordrecht, Netherlands
ISBN-10: 9400730497
Pagini: 248
Ilustrații: XXII, 223 p.
Dimensiuni: 155 x 235 x 13 mm
Greutate: 0.35 kg
Ediția:2010
Editura: SPRINGER NETHERLANDS
Colecția Springer
Seria Lecture Notes in Electrical Engineering
Locul publicării:Dordrecht, Netherlands
Public țintă
ResearchCuprins
MICRO-Architectural Exploration.- A Baseline NoC Architecture.- ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39].- RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40].- Exploring FaultoTolerant Network-on-Chip Architectures [37].- On the Effects of Process Variation in Network-on-Chip Architectures [45].- MACRO-Architectural Exploration.- The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15].- Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43].- A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44].- Digest of Additional NoC MACRO-Architectural Research.- Conclusions and Future Work.
Textul de pe ultima copertă
The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. On-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. The work presented in Network-on-Chip Architectures addresses these issues through a comprehensive exploration of the design space. The design aspects of the NoC are viewed through a penta-faceted prism encompassing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research exploration employs a two-pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads and the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design of NoCs in multi-core architectures.
Caracteristici
A comprehensive study of Network-on-Chip architectures for multi-core chips Analysis of complex interplay between various design evaluation metrics Detailed look at both macro- and micro-architectural design issues Innovative solutions for increased reliability and process variability tolerance