Protecting Chips Against Hold Time Violations Due to Variability
Autor Gustavo Neuberger, Gilson Wirth, Ricardo Reisen Limba Engleză Hardback – 17 oct 2013
The logical consequence of this parameter variation is that circuit characteristics, as delay and power, also become random variables. Because of the delay variability, not all circuits will now have the same performance, but some will be faster and some slower. However, the slowest circuits may be so slow that they will not be appropriate for sale. On the other hand, the fastest circuits that could be sold for a higher price can be very leaky, and also not very appropriate for sale. A main consequence of power variability is that the power consumption of some circuits will be different than expected, reducing reliability, average life expectancy and warranty of products. Sometimes the circuits will not work at all, due to reasons associated with process variations. At the end, these effects result in lower yield and lower profitability.
To understand these effects, it is necessary to study the consequences of variability in several aspects of circuit design, like logic gates, storage elements, clock distribution, and any other that can be affected by process variations. The main focus of this book will be storage elements.
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Specificații
ISBN-13: 9789400724266
ISBN-10: 9400724268
Pagini: 120
Ilustrații: XI, 107 p. 76 illus., 51 illus. in color.
Dimensiuni: 155 x 235 x 12 mm
Greutate: 0.36 kg
Ediția:2014
Editura: SPRINGER NETHERLANDS
Colecția Springer
Locul publicării:Dordrecht, Netherlands
ISBN-10: 9400724268
Pagini: 120
Ilustrații: XI, 107 p. 76 illus., 51 illus. in color.
Dimensiuni: 155 x 235 x 12 mm
Greutate: 0.36 kg
Ediția:2014
Editura: SPRINGER NETHERLANDS
Colecția Springer
Locul publicării:Dordrecht, Netherlands
Public țintă
ResearchCuprins
Introduction, Process Variations and Flip-Flops.- Process Variability.- Flip-Flops and Hold Time Violations.- Circuits Under Test.- Measurement Circuits.- Experimental Results.- Systematic and Random Variablility.- Normality Tests.- Probability of Hold Time Violations.- Protecting Circuits Against Hold Time Violations.- Padding Efficiency Of the Proposed Padding Algorithm.- Final Remarks.
Textul de pe ultima copertă
This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The consequences of variability to several aspects of circuit design, such as logic gates, storage elements, clock distribution, and any other that can be affected by process variations are discussed, with a key focus on storage elements. The authors present a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology. To facilitate an on-wafer test, a measurement circuit with a precision compatible to the speed of the technology is described.
· Provides a comprehensive review of various reliability mechanisms;
· Describes practical modeling and characterization techniques for reliability
· Includes thorough presentation of robust design techniques for major VLSI design units
· Promotes physical understanding with first-principle simulations
· Provides a comprehensive review of various reliability mechanisms;
· Describes practical modeling and characterization techniques for reliability
· Includes thorough presentation of robust design techniques for major VLSI design units
· Promotes physical understanding with first-principle simulations
Caracteristici
Presents a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology Studies the consequences of variability in several aspects of circuit design Focuses specifically on the effects of storage elements on circuit design Includes supplementary material: sn.pub/extras