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Robust SRAM Designs and Analysis de Jawar Singh

Robust SRAM Designs and Analysis

Autor Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan
en Limba Engleză Paperback – 8 aug 2014
This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.
  • Provides a complete and concise introduction to SRAM bitcell design and analysis;
  • Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;
  • Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;
  • Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.
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Specificații

ISBN-13: 9781493902446
ISBN-10: 149390244X
Pagini: 180
Ilustrații: XII, 168 p.
Dimensiuni: 155 x 235 x 9 mm
Greutate: 0.26 kg
Ediția:2013
Editura: Springer
Colecția Springer
Locul publicării:New York, NY, United States

Public țintă

Research

Cuprins

Introduction to SRAM.- Design Metrics of SRAM Bitcell.- Single-ended SRAM Bitcell Design.- 2-Port SRAM Bitcell Design.- SRAM Bitcell Design Using Unidirectional Devices.- NBTI and its Effect on SRAM.

Textul de pe ultima copertă

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.
  • Provides a complete and concise introduction to SRAM bitcell design and analysis;
  • Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;
  • Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;
  • Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.

Caracteristici

Provides a complete and concise introduction to SRAM bitcell design and analysis Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices Emphasizes different trade-offs for achieving the best possible SRAM bitcell design