Unleash the System On Chip using FPGAs and Handel C
Autor Rajanish K. Kamat, Santosh A. Shinde, Vinod G Shelakeen Limba Engleză Hardback – 7 apr 2009
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Specificații
ISBN-13: 9781402093616
ISBN-10: 1402093616
Pagini: 200
Ilustrații: XXIV, 174 p.
Dimensiuni: 155 x 235 x 22 mm
Greutate: 0.46 kg
Ediția:2009
Editura: SPRINGER NETHERLANDS
Colecția Springer
Locul publicării:Dordrecht, Netherlands
ISBN-10: 1402093616
Pagini: 200
Ilustrații: XXIV, 174 p.
Dimensiuni: 155 x 235 x 22 mm
Greutate: 0.46 kg
Ediția:2009
Editura: SPRINGER NETHERLANDS
Colecția Springer
Locul publicării:Dordrecht, Netherlands
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Public țintă
ResearchCuprins
Chapter 1: Introduction. 1.1 Prologue. 1.2 Exceptional Attributes of the SoC Technology. 1.3 Classical taxonomy: a holistic perspective extended towards Integrated Circuits Classification. 1.4 System on Chip (SoC) Term and Scope. 1.5 Constituents of SoC. 1.6 Sprawling Growth of SoC market. 1.7 Choosing the platform, ASIC Vs FPGAs. 1.8 FPGA based Programmable SoC. 1.9 Orientation of the Book.
Chapter 2: Familiarizing with Handel C. 2.1 EDA Tools i.e. Computer Aids for VLSI Design. 2.2 Background of Hardware Description Languages. 2.3 Expressing abstraction at higher levels. 2.4 Where C stands amidst the well established HDLs? 2.5 Introducing Handel C. 2.6 Top Down or Bottom up? 2.7 Handel C: A boon for Software Professionals. 2.8 Handel C Vs ANSI C. 2.9 Handel C Design Flow.
Chapter 3: Sequential logic Design. 3.1 Design Philosophy of Sequential Logic. 3.2 D flip-flop. 3.3 Latch. 3.4 Realization of JK Flip-Flop. 3.5 Cell of Hex counter for Counter Applications. 3.6 Realization of Shift Register for SoC. 3.7 LFSR Core for Security Applications in SoC. 3.8 Clock Scaling and Delay Generation in SoC. 3.9 SoC Data Queuing using FIFO. 3.10 Implementation of Stack though LIFO. 3.11 Soft IP core for Hamming Code.
Chapter 4: Combinational Logic Design. 4.1 Introduction. 4.2 Design Metrics for the Combinational Logic Circuits: SoC Perspective. 4.3 Core of “2 to 4 decoder”. 4.4 “3 to 8 decoder” using hierarchical approach. 4.5 Priority Encoder 4 to 2. 4.6 Soft IP Core of “7 to 3 encoder” Implementation. 4.7 IP core of ‘Parity generator’ for Communication Applications. 4.8 IP Core for Parity checker and error detection for Internet Protocol. 4.9 BCD TO Seven Segment converter. 4.10 Core of Binary to Gray Converter and Applications. 4.11 Realization of IP Core of Gray to Binary Converter. 4.12 Designing Barrel Shifters and their applications.
Chapter 5: Arithmetic core design and Design Reuseof Soft IP Cores. 5.1 Design Reuse Philosophy. 5.2 Advantages of on chip arithmetic. 5.3 Designing Half adder in Handel C. 5.4 Designing Full Adder as a Reusable Core. 5.5 Ripple Carry Adder on Chip. 5.6 Realization of Booth Algorithm using FPGA. 5.7 Building 8 bit ALU. 5.7 Third Party Tool Interface with Handel C. 5.8 Xilinx EDK Interface with Cores developed through Handel C.
Chapter 6: Rapid Prototyping of the Soft IP cores on FPGA. 6.1 Prototyping Philosophy. 6.2 Design and Prototyping of a Fuzzy Controller. 6.3 TCP/IP Packet Splitter Implementation Using Mixed Design Flow. 6.4. Linear Congruential Random Number Generator. 6.5 Implementation of Reusable Soft IP core of Blowfish Cipher.
Chapter 7: Soft Processor Core for Accelerated Embedded Design. 7.1 Building SoC for temperature control application using Picoblaze. 7.2 Hardware Software Codesign of SoC with built in Position Algorithm.
References. Index of Tables. Index of Figures. Index of Programs.
Chapter 2: Familiarizing with Handel C. 2.1 EDA Tools i.e. Computer Aids for VLSI Design. 2.2 Background of Hardware Description Languages. 2.3 Expressing abstraction at higher levels. 2.4 Where C stands amidst the well established HDLs? 2.5 Introducing Handel C. 2.6 Top Down or Bottom up? 2.7 Handel C: A boon for Software Professionals. 2.8 Handel C Vs ANSI C. 2.9 Handel C Design Flow.
Chapter 3: Sequential logic Design. 3.1 Design Philosophy of Sequential Logic. 3.2 D flip-flop. 3.3 Latch. 3.4 Realization of JK Flip-Flop. 3.5 Cell of Hex counter for Counter Applications. 3.6 Realization of Shift Register for SoC. 3.7 LFSR Core for Security Applications in SoC. 3.8 Clock Scaling and Delay Generation in SoC. 3.9 SoC Data Queuing using FIFO. 3.10 Implementation of Stack though LIFO. 3.11 Soft IP core for Hamming Code.
Chapter 4: Combinational Logic Design. 4.1 Introduction. 4.2 Design Metrics for the Combinational Logic Circuits: SoC Perspective. 4.3 Core of “2 to 4 decoder”. 4.4 “3 to 8 decoder” using hierarchical approach. 4.5 Priority Encoder 4 to 2. 4.6 Soft IP Core of “7 to 3 encoder” Implementation. 4.7 IP core of ‘Parity generator’ for Communication Applications. 4.8 IP Core for Parity checker and error detection for Internet Protocol. 4.9 BCD TO Seven Segment converter. 4.10 Core of Binary to Gray Converter and Applications. 4.11 Realization of IP Core of Gray to Binary Converter. 4.12 Designing Barrel Shifters and their applications.
Chapter 5: Arithmetic core design and Design Reuseof Soft IP Cores. 5.1 Design Reuse Philosophy. 5.2 Advantages of on chip arithmetic. 5.3 Designing Half adder in Handel C. 5.4 Designing Full Adder as a Reusable Core. 5.5 Ripple Carry Adder on Chip. 5.6 Realization of Booth Algorithm using FPGA. 5.7 Building 8 bit ALU. 5.7 Third Party Tool Interface with Handel C. 5.8 Xilinx EDK Interface with Cores developed through Handel C.
Chapter 6: Rapid Prototyping of the Soft IP cores on FPGA. 6.1 Prototyping Philosophy. 6.2 Design and Prototyping of a Fuzzy Controller. 6.3 TCP/IP Packet Splitter Implementation Using Mixed Design Flow. 6.4. Linear Congruential Random Number Generator. 6.5 Implementation of Reusable Soft IP core of Blowfish Cipher.
Chapter 7: Soft Processor Core for Accelerated Embedded Design. 7.1 Building SoC for temperature control application using Picoblaze. 7.2 Hardware Software Codesign of SoC with built in Position Algorithm.
References. Index of Tables. Index of Figures. Index of Programs.
Textul de pe ultima copertă
The last two decades have witnessed the overhauling growth in microelectronics and it has emerged as a major new technological force shaping our everyday lives. Apart from the ubiquitous penetration in the social life, the microelectronics is going though a paradigm shift from the VLSI to personal computers, mobile devices and finally converging to single-chip solutions embedded with the intelligence in both hardware and software form. It is undisputed fact that the System-on-a-chip (SoC) is revitalizing the design of integrated circuits due to the unprecedented levels of integration possible and has become the pervasive next generation revolution in microelectronics and Chip Design.
The proliferation of ‘SoC’ have made most of the prognosticators to bet that it is going to sustain and thrive the accelerated growth in the semiconductor market. However, the designers are agonized about the resuscitation of the Moore’s law that has delivered consistently since about 1975, inspite of changing the design perceptions from transistors to IP cores, functional and structural diversification which is popularly known as “More than Moore”. In nutshell, the ‘Halcyon Days’ enjoyed by the VLSI industry are behind us and there is constant quest for development of affluent design methodologies for addressing the narrow market windows and accelerated obsolescence cycles that naturally impose reduced development times for the devices in the new era belonging to SoCs.
Unleash the System On Chip using FPGAs and Handel C is an attempt to empower the design community by delivering the ‘know-how’ developed by the authors through their vast development experience in the areas of ‘VLSI Design’, Embedded Systems, ‘Hardware Software Co-Design’, ‘Reconfigurable System Design’ and ‘Network On Chip Design’. The book effectively showcases building the SoC from ‘Concept to Product’. With the foundingconception that the future SoC designer is today’s software designer, the book laid emphasis on ‘C’ based methodology which is considered at a much higher level of abstraction. The emerging ‘hardware-software functional alloy’ perception of the SoCs is comprehended by leveraging the bottom up (i.e. design reuse) approach by edifying with the soft IP cores developed in Handel C which is also the pragmatic approach to bridge the gap between productivity, yield, quality, specifications (temporal and spatial), verification and prototyping. The hard design process of SoC is exemplified by a synergic approach of combining the flexibility and performance of FPGAs with the rich set of available soft IP cores developed in Handel C. More complex design approaches such as ‘partial reconfiguration’, ‘concurrent hardware software SoC realization’ are addressed by using the Xilinx EDK toolset. With the growing trend of SoC designer becoming the ‘network engineer’ and vice versa, few case studies have devoted towards building the ‘Network on Chip (NoC)’. System optimization and quick verification is dealt in this book by adopting co-simulation and third party tool integration such as ModelSim. Other diversified, still interesting SoC case studies that will definitely help the designers in building intelligent chips are fuzzy logic controllers, code converters, arithmetic on chip etc. Control system SoCs are realized in this book by using the Soft IP processor cores such as ‘picoblaze’. This will definitely open a window for the Embedded Developers pursuing their one chip design endeavors. The complicated concepts such as design flow with respect to the Handel C, EDK etc. are simplified by giving actual screenshots and step by step approach, so that a mere walk though them will give a “Hands-On’ approach. Finally through 35 working Handel C cores, seven chapters and 128 references chosen from the selected whitepapers, research papers and WEB URLs will definitely empower the SoC veteran as well as beginner in not only getting acquainted with the innovative design methodologies of building the SoCs, but also opens a new door of research and development and infinite set of futures in this ever-growing enabling technology of this century.
The proliferation of ‘SoC’ have made most of the prognosticators to bet that it is going to sustain and thrive the accelerated growth in the semiconductor market. However, the designers are agonized about the resuscitation of the Moore’s law that has delivered consistently since about 1975, inspite of changing the design perceptions from transistors to IP cores, functional and structural diversification which is popularly known as “More than Moore”. In nutshell, the ‘Halcyon Days’ enjoyed by the VLSI industry are behind us and there is constant quest for development of affluent design methodologies for addressing the narrow market windows and accelerated obsolescence cycles that naturally impose reduced development times for the devices in the new era belonging to SoCs.
Unleash the System On Chip using FPGAs and Handel C is an attempt to empower the design community by delivering the ‘know-how’ developed by the authors through their vast development experience in the areas of ‘VLSI Design’, Embedded Systems, ‘Hardware Software Co-Design’, ‘Reconfigurable System Design’ and ‘Network On Chip Design’. The book effectively showcases building the SoC from ‘Concept to Product’. With the foundingconception that the future SoC designer is today’s software designer, the book laid emphasis on ‘C’ based methodology which is considered at a much higher level of abstraction. The emerging ‘hardware-software functional alloy’ perception of the SoCs is comprehended by leveraging the bottom up (i.e. design reuse) approach by edifying with the soft IP cores developed in Handel C which is also the pragmatic approach to bridge the gap between productivity, yield, quality, specifications (temporal and spatial), verification and prototyping. The hard design process of SoC is exemplified by a synergic approach of combining the flexibility and performance of FPGAs with the rich set of available soft IP cores developed in Handel C. More complex design approaches such as ‘partial reconfiguration’, ‘concurrent hardware software SoC realization’ are addressed by using the Xilinx EDK toolset. With the growing trend of SoC designer becoming the ‘network engineer’ and vice versa, few case studies have devoted towards building the ‘Network on Chip (NoC)’. System optimization and quick verification is dealt in this book by adopting co-simulation and third party tool integration such as ModelSim. Other diversified, still interesting SoC case studies that will definitely help the designers in building intelligent chips are fuzzy logic controllers, code converters, arithmetic on chip etc. Control system SoCs are realized in this book by using the Soft IP processor cores such as ‘picoblaze’. This will definitely open a window for the Embedded Developers pursuing their one chip design endeavors. The complicated concepts such as design flow with respect to the Handel C, EDK etc. are simplified by giving actual screenshots and step by step approach, so that a mere walk though them will give a “Hands-On’ approach. Finally through 35 working Handel C cores, seven chapters and 128 references chosen from the selected whitepapers, research papers and WEB URLs will definitely empower the SoC veteran as well as beginner in not only getting acquainted with the innovative design methodologies of building the SoCs, but also opens a new door of research and development and infinite set of futures in this ever-growing enabling technology of this century.
Caracteristici
Addresses the proliferation of ‘SoC’ a technology of immense importance Ready made Soft IP Cores given in Handel C Presents Know-how for accelerated design and enhanced productivity Design case studies realized using Industry Standard and Leading EDA Tools Covers important concepts such as Network On Chip, Fuzzy Controller, IP cores etc.