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A Roadmap for Formal Property Verification de Pallab Dasgupta

A Roadmap for Formal Property Verification

Autor Pallab Dasgupta
en Limba Engleză Hardback – 5 iul 2006
Integrating formal property verification (FPV) into an existing design process raises several interesting questions. Have I written enough properties? Have I written a consistent set of properties? What should I do when the FPV tool runs into capacity issues? This book develops the answers to these questions and fits them into a roadmap for formal property verification – a roadmap that shows how to glue FPV technology into the traditional validation flow. A Roadmap for Formal Property Verification explores the key issues in this powerful technology through simple examples – you do not need any background on formal methods to read most parts of this book.
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Specificații

ISBN-13: 9781402047572
ISBN-10: 1402047576
Pagini: 251
Ilustrații: XIV, 252 p.
Dimensiuni: 155 x 235 x 17 mm
Greutate: 0.62 kg
Ediția:2006
Editura: SPRINGER NETHERLANDS
Colecția Springer
Locul publicării:Dordrecht, Netherlands

Public țintă

Research

Cuprins

Languages for Temporal Properties.- How Does the Property Checker Work?.- Is My Specification Consistent?.- Have I Written Enough Properties?.- Design Intent Coverage.- Test Generation Games.- A Roadmap for Formal Property Verification.

Recenzii

"This book is a "must-read" for anyone who needs a broad and deep understanding of  assertion-based verification technology and methodology. It gives an in-depth overview of the logic behind, and algorithms for, reasoning about design behavior using assertions. The book also presents advanced methods for checking consistency and coverage of an assertion-based specification, for maintaining completeness of a specification as it is refined, and for leveraging assertions for automatic test generation in constrained random simulation.
Detailing both established practice and recent developments, "A Roadmap for Formal Property Verification" is a valuable reference for insight into both the present and the future of assertion-based verification." (Erich Marschner, Senior Architect, Systems and Functional Verification, Cadence Design Systems, and Co-Chair, Accellera Formal Verification Technical Committee (FVTC)

Notă biografică

The author leads the Formal Verification Group at the Indian Institute of Technology, Kharagpur (http://www.facweb.iitkgp.ernet.in/~pallab/forverif.html). He has collaborations with leading companies, including Intel, Sun Microsystems, Synopsys, Texas Instruments, National Semiconductors, General Motors, Interra Systems and Virtio Corp, on developing formal methods for design verification. The author is a senior member of IEEE.

Caracteristici

FPV methods - presented conceptually Architecting assertion suites with System Verilog Assertions Formal verification coverage Consistency issues in formal specifications Design Intent Coverage Intelligent test generation from formal specifications