Advanced Low-Power Digital Circuit Techniques: The Springer International Series in Engineering and Computer Science, cartea 405
Autor Muhammad S. Elrabaa, Issam S. Abu-Khater, Mohamed I. Elmasryen Limba Engleză Paperback – 25 sep 2012
Advanced Low-Power Digital Circuit Techniques is a real designer's book. It investigates alternative circuit styles, as well as architectural alternatives, and gives quantitative results for comparison in realistic technologies. Several of the circuits presented have been fabricated so that simulations can be checked. The circuits covered are the most important building blocks for many designs, so the text will be of direct use to designers. MOS designs are covered, as well as BiCMOS, and there are several novel circuits.
Toate formatele și edițiile | Preț | Express |
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Paperback (1) | 914.05 lei 6-8 săpt. | |
Springer Us – 25 sep 2012 | 914.05 lei 6-8 săpt. | |
Hardback (1) | 920.17 lei 6-8 săpt. | |
Springer Us – 31 mai 1997 | 920.17 lei 6-8 săpt. |
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Specificații
ISBN-13: 9781461346364
ISBN-10: 1461346363
Pagini: 224
Ilustrații: XXV, 197 p.
Dimensiuni: 155 x 235 x 12 mm
Greutate: 0.32 kg
Ediția:Softcover reprint of the original 1st ed. 1997
Editura: Springer Us
Colecția Springer
Seria The Springer International Series in Engineering and Computer Science
Locul publicării:New York, NY, United States
ISBN-10: 1461346363
Pagini: 224
Ilustrații: XXV, 197 p.
Dimensiuni: 155 x 235 x 12 mm
Greutate: 0.32 kg
Ediția:Softcover reprint of the original 1st ed. 1997
Editura: Springer Us
Colecția Springer
Seria The Springer International Series in Engineering and Computer Science
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
1 Low-Power VLSI Design.- 1.1 Power Estimation and Evaluation for Digital VLSI Circuits.- 1.2 Low-Power Impact on Process and Technology.- 1.3 This Book.- References.- 2 Low-Power High-Performance Adders.- 2.1 Introduction.- 2.2 Architecture.- 2.3 Circuit Design and Implementation.- 2.4 Optimization Using Variable Block Size Combination.- 2.5 Simulation Strategy.- 2.6 Circuit performance.- 2.7 Layout Strategy.- 2.8 Experimental Results.- 2.9 Summary.- References.- Low-Power High-Performance Multipliers.- 3.1 Introduction.- 3.2 Review of Parallel Multipliers.- 3.3 Multiplier Architecture and Simulation Method.- 3.4 Multiplier Cell.- 3.5 Booth Encoder.- 3.6 Add Cell.- 3.7 CSA.- 3.8 6-Bit Multiplier.- 3.9 Summary.- References.- Low-Power Register File.- 4.1 Introduction.- 4.2 Architecture and Simulation Procedure.- 4.3 Memory Cell Circuit.- 4.4 Write Circuitry.- 4.5 Read Circuitry.- 4.6 Decoder Circuit.- 4.7 32x32-bit Register File.- 4.8 Summary.- References.- Low-Power Embedded Bicmos/ECL Srams.- 5.1 Introduction.- 5.2 16 Mb+ SRAMs Front-end Optimization.- 5.3 The Novel W-ORing and Level-Translation Circuits.- 5.4 The Novel Self-Resetting WL Decoder and Driver.- 5.5 The Novel Latched Sense-Amplifier.- 5.6 Chapter Summary.- References.- BICMOS On-Chip Drivers.- 6.1 Introduction.- 6.2 The Novel Full-Swing BiCMOS Circuit Technique.- Performance Comparisons.- 6.4 Design of the Feedback Circuitry.- 6.5 Chapter Summary.- References.- Inter-Chip Low-Voltage-Swing Transceivers.- 7.1 Introduction.- 7.2 Low-Power ECL/CML Dynamic Circuit Techniques.- 7.3 The Universal Transceiver (Receiver/Driver).- 7.4 Chapter Summary.- References.