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Application-Specific Mesh-based Heterogeneous FPGA Architectures de Husain Parvez

Application-Specific Mesh-based Heterogeneous FPGA Architectures

Autor Husain Parvez, Habib Mehrez
en Limba Engleză Hardback – 17 noi 2010
This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures.
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Specificații

ISBN-13: 9781441979278
ISBN-10: 1441979271
Pagini: 166
Ilustrații: XVII, 150 p.
Dimensiuni: 155 x 235 x 23 mm
Greutate: 0.42 kg
Ediția:2011
Editura: Springer
Colecția Springer
Locul publicării:New York, NY, United States

Public țintă

Research

Cuprins

Introduction.- State of the Art.- FPGA Layout Generation.- ASIF: Application Specific Inflexible FPGA.- ASIF using Heterogeneous Logic Blocks.- ASIF Hardware Generation.- Conclusion and Future Lines of Research.

Textul de pe ultima copertă

Low volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However, the flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs. Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption.
This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures.  It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required.  Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures.
  • Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures;
  • Describes state-of-the-art techniques for reducing area requirements in FPGA architectures;
  • Enables reduction in power required and increase in performance.

Caracteristici

Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures Describes state-of-the-art techniques for reducing area requirements in FPGA architectures Enables reduction in power required and increase in performance Includes supplementary material: sn.pub/extras