Cantitate/Preț
Produs

Design Techniques for Mash Continuous-Time Delta-Sigma Modulators

Autor Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Jose Silva-Martinez
en Limba Engleză Hardback – 11 apr 2018
This book describes a circuit architecture for converting real analog signals into a digital format, suitable for digital signal processors. This architecture, referred to as multi-stage noise-shaping (MASH) Continuous-Time Sigma-Delta Modulators (CT-ΔΣM), has the potential to provide better digital data quality and achieve better data rate conversion with lower power consumption.  The authors not only cover MASH continuous-time sigma delta modulator fundamentals, but also provide a literature review that will allow students, professors, and professionals to catch up on the latest developments in related technology.
Citește tot Restrânge

Toate formatele și edițiile

Toate formatele și edițiile Preț Express
Paperback (1) 62393 lei  22-36 zile
  Springer International Publishing – 19 dec 2018 62393 lei  22-36 zile
Hardback (1) 63015 lei  43-57 zile
  Springer International Publishing – 11 apr 2018 63015 lei  43-57 zile

Preț: 63015 lei

Preț vechi: 74135 lei
-15% Nou

Puncte Express: 945

Preț estimativ în valută:
12060 12527$ 10017£

Carte tipărită la comandă

Livrare economică 03-17 februarie 25

Preluare comenzi: 021 569.72.76

Specificații

ISBN-13: 9783319772240
ISBN-10: 3319772244
Pagini: 310
Ilustrații: XVI, 208 p. 184 illus., 71 illus. in color.
Dimensiuni: 155 x 235 mm
Greutate: 0.49 kg
Ediția:1st ed. 2018
Editura: Springer International Publishing
Colecția Springer
Locul publicării:Cham, Switzerland

Cuprins

Introduction.- Analog-To-Digital and Digital-To-Analog Converters.- Delta-Sigma Modulators.- Design Considerations Of Mash CT-ΔΣM.- A 43 mW MASH 2-2 CT ΔΣ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40nm CMOS.- A 50-MHz BW 67.3-dB SNDR MASH 1-1-1 CT ΔΣ Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.- A 4-Bit Continuous-Time ΔΣ Modulator with Fully Digital Quantizer Noise Reduction Algorithm Employing a 7-bit Quantizer.- Conclusion.

Notă biografică

Qiyuan Liu is a Senior Engineer at Qualcomm. Alexander Edward is a Senior Engineer at Intel.
Carlos Briseno-Vidrios is a Senior Engineer at Silicon Labs.
Jose Silva-Martinez got his PhD degree from the Katholieke Universiteit Leuven, Belgium in 1992. He currently holds the rank of Texas Instruments Professor in Analog Engineering at the Department of ECE, Texas A&M University. Dr. Silva-Martinez is an IEEE-Fellow and member of the 2013-2014 CASS Distinguish Lecture Program. His record of publications show over 100 journals and 160 conferences, 2 books and 12 book chapters and 1 patent. He is co-author of the papers that received the 2011 Best Student Paper Award, IEEE MWCAS, the 2003 Best Student Paper Award, IEEE RF-IC, and recipient of the 1990 Best Paper Award, European Solid-State Circuits Conference (ESSCIRC). He got the 2005 Outstanding Professor Award by the ECE Department, Texas A&M University, 2005; co-Advised in Testing techniques the student who was Winner ofthe 2005 Best Doctoral Thesis Award, presented by the IEEE Test Technology Technical Council (TTTC), IEEE Computer Society.

Textul de pe ultima copertă

This book describes a circuit architecture for converting real analog signals into a digital format, suitable for digital signal processors. This architecture, referred to as multi-stage noise-shaping (MASH) Continuous-Time Sigma-Delta Modulators (CT-ΔΣM), has the potential to provide better digital data quality and achieve better data rate conversion with lower power consumption.  The authors not only cover MASH continuous-time sigma delta modulator fundamentals, but also provide a literature review that will allow students, professors, and professionals to catch up on the latest developments in related technology.

Caracteristici

Provides first book focusing on MASH CT-?SMs, including detailed design fundamentals Covers both circuit- and system-level design considerations and provides design methodologies and examples Enables readers to implement architectures designed to face the challenges of the next generation of wireless communication systems that demand wider bandwidth with better resolution