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Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip de Pascal Meinerzhagen

Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

Autor Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
en Limba Engleză Hardback – 14 iul 2017
This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
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Specificații

ISBN-13: 9783319604015
ISBN-10: 3319604015
Pagini: 160
Ilustrații: IX, 146 p. 84 illus. in color.
Dimensiuni: 155 x 235 mm
Greutate: 0.4 kg
Ediția:1st ed. 2018
Editura: Springer International Publishing
Colecția Springer
Locul publicării:Cham, Switzerland

Cuprins

Motivation.- Introduction to Gain-Cell Based eDRAMs (GC-eDRAMs).- GC-eDRAMs Operated at Scaled Supply Voltages.- Near-VT GC-eDRAM Implementations with Extended Retention Times.- Aggressive Technology and Voltage Scaling (to Sub-VT Domain).- Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications.- 4T Gain-Cell with Internal-Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes.- Multilevel GC-eDRAM (MLGC-eDRAM).- Soft Error Tolerant Low Power 4T Gain-Cell Array with Multi-Bit Error Detection and Correction.- Conclusions.

Notă biografică

Dr. Pascal Meinerzhagen is a Senior Research Scientist at Intel Labs, Intel Corporation, performing research into energy-efficient, error-resilient circuits and systems in high-performance FinFET CMOS technology.
Dr. Adam Teman is a tenure track Senior Lecturer and co-director of the Emerging NanoScaled Integrated Circuits and Systems (EnICS) Labs in the Faculty of Engineering at Bar-Ilan Univeristy. His research interests include energy-efficient digital circuit design with an emphasis on embedded memories and efficient physical implementation of VLSI systems.
Robert Giterman is a researcher Ph.D. student at the Emerging Nanoscaled Intergrated Circuits and Systems (EnICS) Labs in Bar Ilan University, guided by Prof. Alexander Fish and Dr. Adam Teman. He received the B.Sc. degree in electrical engineering from Ben-Gurion University, Be’er Sheva, Israel, in 2013. He completed the M.Sc. degree at Ben-Gurion University in 2014 as part of a fast track program for outstanding students. Mr. Giterman’s research interests include embedded DRAM design and optimization for low power and high performance operation, SRAM design with an emphasis on improved stability, error-correction and fault-tolerant circuits and development of hardware-security oriented embedded memories for use in low-power applications and high-end processors. As part of his research, he led several full test chip integrations and tape out. He has authored/co-authored 15 journal articles and international conference papers and 3 patent applications, and has presented his research at a number of international conferences. In 2014, he was awarded the presidential scholarship for outstanding Doctorate students.
Noa Edri is a design and verification SoC engineer at Nanoscaled Intergrated Circuits and Systems (EnICS) Labs in Bar Ilan University. She received her B.Sc. in Electrical and Computer Engineering from Ben Gurion University, Israel, in 2012. She completed her M.Sc. at Bar-Ilan University in 2015 under the guidance of Prof. Alex Fish. Her M.Sc. thesis focused on embedded DRAM optimization for low power and developing system methodology for low data retention voltage in SRAM.
Prof. Andreas Burg is Professor and Director of the Telecommunications Circuits Laboratory at EPFL. His research interests range from transistor-level CMOS design (mostly for embedded memories) to energy-efficient embedded systems to the design of algorithms and architectures for VLSI Signal Processing and circuits and systems for wireless communications.
Prof. Alexander Fish is a Professor, head of the NanoElectronics Track and founder of the Emerging NanoScaled Integrated Circuits and Systems (EnICS) Labs in the Faculty of Engineering at Bar-Ilan Univeristy. His research interests include development of energy efficient “smart” CMOS image sensors, ultra low power SRAM, DRAM and Flash memory arrays and energy efficient design techniques for low voltage digital and analog VLSI chips.
 

Textul de pe ultima copertă

This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.

Caracteristici

Provides novel gain-cell embedded DRAM (GC-eDRAM) designs for various low-power VLSI SoC applications; Models the statistical retention time distribution of GC-eDRAM and validates the model by silicon measurements; Describes various memory optimizations, including unique bitcell and assist circuits, targeted at increased retention time and reduced power consumption while hardly compromising area and speed; Demonstrates several new techniques at the circuit, architectural, and algorithmic levels which enable NTV and subthreshold operation of GC-eDRAM, implementation of GC-eDRAM in aggressively scaled CMOS nodes, as well as soft-error tolerance. Includes supplementary material: sn.pub/extras