Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications: The Springer International Series in Engineering and Computer Science, cartea 139
Autor Patrick C. McGeer, Robert K. Braytonen Limba Engleză Paperback – 30 sep 2012
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Paperback (1) | 629.65 lei 43-57 zile | |
Springer Us – 30 sep 2012 | 629.65 lei 43-57 zile | |
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Springer Us – 31 mai 1991 | 635.96 lei 43-57 zile |
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Specificații
ISBN-13: 9781461367680
ISBN-10: 1461367689
Pagini: 240
Ilustrații: XXIII, 212 p.
Dimensiuni: 155 x 235 x 13 mm
Greutate: 0.34 kg
Ediția:Softcover reprint of the original 1st ed. 1991
Editura: Springer Us
Colecția Springer
Seria The Springer International Series in Engineering and Computer Science
Locul publicării:New York, NY, United States
ISBN-10: 1461367689
Pagini: 240
Ilustrații: XXIII, 212 p.
Dimensiuni: 155 x 235 x 13 mm
Greutate: 0.34 kg
Ediția:Softcover reprint of the original 1st ed. 1991
Editura: Springer Us
Colecția Springer
Seria The Springer International Series in Engineering and Computer Science
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
1 Introduction.- 1.1 Timing Analysis of Circuits.- 1.2 The General False Path Problem.- 1.3 A Note on Notation.- 1.4 Logic Notation.- 1.5 Outline.- 2 The False Path Problem.- 2.1 Introduction.- 2.2 Dynamic Timing Analysis.- 2.3 Viable Paths.- 2.4 Symmetric Networks and Monotonicity.- 2.5 Viability Under Network Transformations.- 2.6 The Viability Function.- 2.7 Summary.- 3 False Path Detection Algorithms.- 3.1 Generic False Path Detection Algorithm.- 3.2 Viability Analysis Procedure.- 3.3 Dynamic Programming Algorithm Example.- 3.4 Finding all the Longest Viable Paths.- 3.5 Recent Work.- 4 System Considerations and Approximations.- 4.1 Approximation Theory and Practice.- 4.2 “Weak” Viability.- 4.3 The Brand-Iyengar Procedure.- 4.4 The Du-Yen-Ghanta Criteria.- 4.5 The Chen-Du Criterion.- 4.6 More Macroexpansion Transformations.- 4.7 Biased Satisfiability Tests.- 4.8 Axes of Approximation.- 4.9 The Lllama Timing Environment.- 4.10 Experimental Results.- 5 Hazard Prevention in Combinational Circuits.- 5.1 Introduction.- 5.2 Hazards.- 5.3 The Boolean n-Space.- 5.4 The SDC Set and Restricted Cubes.- 5.5 Ordering The Inputs.- 6 Timing Analysis in Hazard-Free Networks.- 6.1 Introduction.- 6.2 Robustness of Dynamic Sensitization.- 6.3 The Dynamic Sensitization Function.- 6.4 Algorithms.- 6.5 Conclusion.- A Complexity Results.- A.1 An Introduction to Polynomial Reducibility.- B A Family of Operators.- C Fast Procedures for Computing Dataflow Sets.- C.1 Introduction.- C.2 Terminology.- C.3 The New Approach.- C.4 Computations.- C.4.1 Basic Algorithms.- C.4.2 Transitivity.- C.4.4 Evaluation Algorithms.- C.5 Correctness.- C.6 Complexity Analysis.- C.7 Efficiency.- C.8 Sparse Matrix Implementation.- C.9 An Improvement.- C.10 Results.- C.11 Extensions.- C.11.1 Extending ArbitraryCubes.- C.11.2 The Fanout Care Set and the Test Function.- D Precharged, Unate Circuits.