Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications
Autor Gaurav Singh, Sandeep Kumar Shuklaen Limba Engleză Paperback – 18 sep 2014
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Specificații
ISBN-13: 9781489987020
ISBN-10: 1489987029
Pagini: 184
Ilustrații: XXX, 154 p.
Dimensiuni: 155 x 235 x 10 mm
Greutate: 0.27 kg
Ediția:2010
Editura: Springer
Colecția Springer
Locul publicării:New York, NY, United States
ISBN-10: 1489987029
Pagini: 184
Ilustrații: XXX, 154 p.
Dimensiuni: 155 x 235 x 10 mm
Greutate: 0.27 kg
Ediția:2010
Editura: Springer
Colecția Springer
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
Related Work.- Background.- Low-Power Problem Formalization.- Heuristics for Power Savings.- Complexity Analysis of Scheduling in CAOS-Based Synthesis.- Dynamic Power Optimizations.- Peak Power Optimizations.- Verifying Peak Power Optimizations Using SPIN Model Checker.- Epilogue.
Textul de pe ultima copertă
Low Power Hardware Synthesis from Concurrent Action-Oriented SpecificationsGaurav SinghSandeep K. Shukla This book introduces novel techniques for generating low-power hardware from a high-level description of a design in terms of Concurrent Action-Oriented Specifications (CAOS). It also describes novel techniques for formal verification of such designs. It will provide the readers with definitions of various power optimization and formal verification problems related to CAOS-based synthesis, necessary background concepts, techniques to generate hardware according to the design’s power requirements, and detailed experimental results obtained by applying the techniques introduced on realistic hardware designs. •Presents detailed analysis of various power optimization problems associated with high-level synthesis, as well as novel techniques for reducing power consumption of hardware designs at a higher level of abstraction;•Discusses various formal verification issues associated with synthesizing different possible versions of a hardware design (differing in their latency, area, and/or power consumption);•Includes detailed experimental results obtained by applying the techniques introduced on benchmark hardware designs.
Caracteristici
Presents detailed analysis of various power optimization problems associated with high-level synthesis, as well as novel techniques for reducing power consumption of hardware designs at higher level of abstraction Discusses various formal verification issues associated with synthesizing different possible versions of a hardware design (differing in their latency, area, and/or power consumption)