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Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them

Autor Stuart Sutherland, Don Mills
en Limba Engleză Hardback – 26 iun 2007
In programming, “Gotcha” is a well known term. A gotcha is a language feature, which, if misused, causes unexpected - and, in hardware design, potentially disastrous - behavior. The purpose of this book is to enable engineers to write better Verilog/SystemVerilog design and verification code, and to deliver digital designs to market more quickly.
This book shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize these common coding mistakes, and know how to avoid them. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug the errors.
This book is unique because while there are many books that teach the language, and a few that try to teach coding style, no other book addresses how to recognize and avoid coding errors with these languages.
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Specificații

ISBN-13: 9780387717142
ISBN-10: 0387717145
Pagini: 214
Ilustrații: XXII, 218 p.
Dimensiuni: 155 x 235 x 18 mm
Greutate: 0.52 kg
Ediția:2007
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States

Public țintă

Professional/practitioner

Cuprins

Introduction, What Is A Gotcha?.- Declaration and Literal Number Gotchas.- RTL Modeling Gotchas.- Operator Gotchas.- General Programming Gotchas.- Object Oriented and Multi-Threaded Programming Gotchas.- Randomization, Coverage and Assertion Gotchas.- Tool Compatibility Gotchas.

Caracteristici

Includes over 100 common coding mistakes that can be made with Verilog and SystemVerilog Explains the symptoms of the error, the rules that cover the error, and how to avoid the error Addresses how to recognize and avoid coding errors withing Verilog and SystemVerilog