Correct Hardware Design and Verification Methods: 10th IFIP WG10.5 Advanced Research Working Conference, CHARME'99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings: Lecture Notes in Computer Science, cartea 1703
Editat de Laurence Pierre, Thomas Kropfen Limba Engleză Paperback – 15 sep 1999
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Specificații
ISBN-13: 9783540665595
ISBN-10: 3540665595
Pagini: 388
Ilustrații: XII, 376 p.
Dimensiuni: 155 x 235 x 20 mm
Greutate: 0.54 kg
Ediția:1999
Editura: Springer Berlin, Heidelberg
Colecția Springer
Seria Lecture Notes in Computer Science
Locul publicării:Berlin, Heidelberg, Germany
ISBN-10: 3540665595
Pagini: 388
Ilustrații: XII, 376 p.
Dimensiuni: 155 x 235 x 20 mm
Greutate: 0.54 kg
Ediția:1999
Editura: Springer Berlin, Heidelberg
Colecția Springer
Seria Lecture Notes in Computer Science
Locul publicării:Berlin, Heidelberg, Germany
Public țintă
ResearchCuprins
Invited Talks.- Esterel and Jazz : Two Synchronous Languages for Circuit Design.- Design Process of Embedded Automotive Systems—Using Model Checking for Correct Specifications.- Proof of Microprocessors.- A Proof of Correctness of a Processor Implementing Tomasulo’s Algorithm without a Reorder Buffer.- Formal Verification of Explicitly Parallel Microprocessors.- Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic.- Model Checking.- Model Checking TLA+ Specifications.- Efficient Decompositional Model Checking for Regular Timing Diagrams.- Vacuity Detection in Temporal Model Checking.- Formal Methods and Industrial Applications.- Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaard.- Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors.- Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics.- Abstraction and Compositional Techniques.- From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking.- Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction.- Abstract BDDs: A Technique for Using Abstraction in Model Checking.- Theorem Proving Related Approaches.- Formal Synthesis at the Algorithmic Level.- Xs Are for Trajectory Evaluation, Booleans Are for Theorem Proving.- Verification of Infinite State Systems by Compositional Model Checking.- Symbolic Simulation/Symbolic Traversal.- Formal Verification of Designs with Complex Control by Symbolic Simulation.- Hints to Accelerate Symbolic Traversal.- Specification Languages and Methodologies.- Modeling and Checking Networks of CommunicatingReal-Time Processes.- ”Have I Written Enough Properties?” - A Method of Comparison Between Specification and Implementation.- Program Slicing of Hardware Description Languages.- Posters.- Results of the Verification of a Complex Pipelined Machine Model.- Hazard—Freedom Checking in Speed—Independent Systems.- Yet Another Look at LTL Model Checking.- Verification of Finite-State-Machine Refinements Using a Symbolic Methodology.- Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars.- A Systematic Incrementalization Technique and Its Application to Hardware Design.- Bisimulation and Model Checking.- Circular Compositional Reasoning about Liveness.- Symbolic Simulation of Microprocessor Models Using Type Classes in Haskell.- Exploiting Retiming in a Guided Simulation Based Validation Methodology.- Fault Models for Embedded Systems.- Validation of Object-Oriented Concurrent Designs by Model Checking.
Caracteristici
Includes supplementary material: sn.pub/extras