Analog Circuit Design: (X)DSL and other Communication Systems; RF MOST Models; Integrated Filters and Oscillators
Editat de Willy M.C. Sansen, Johan Huijsing, Rudy J. van de Plasscheen Limba Engleză Hardback – 31 oct 1999
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Specificații
ISBN-13: 9780792386223
ISBN-10: 0792386221
Pagini: 382
Ilustrații: VIII, 382 p.
Dimensiuni: 156 x 234 x 28 mm
Greutate: 0.75 kg
Ediția:1999
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
ISBN-10: 0792386221
Pagini: 382
Ilustrații: VIII, 382 p.
Dimensiuni: 156 x 234 x 28 mm
Greutate: 0.75 kg
Ediția:1999
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
I: (X)DSL and other Communication Systems.- Building an ADSL Modem, the Basics.- ADSL CODEC Architecture that Minimizes DSP Computational Burden.- A 3. 3 V 15-bit Delta-Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL-Applications.- Transmitter & Receiver Clipping Mitigation in DMT Transceivers.- Survey of the State of the Art Analog Front End Circuit Techniques for ADSL.- II: RF MOST Models.- RF CMOS Modelling.- Physics Based Accurate Extraction of LEFF and RS for Deep Submicron Mosfets.- Recent Developments in BSIM for CMOS RF ac and Noise Modeling.- MOS Transistor Modeling Issues for RF Circuit Design.- RF Modelling and characterisation of SOI and bulk MOSFET’s.- Microwave Noise Modeling of CMOS Transistors.- III: Integrated Filters and Oscillators.- Specific Aspects of high frequency Gm-C filters.- Tunable bipolar and biCMOS Gm-C filters for high-frequencies.- High Speed Analog Filters Using Scaled CMOS Technology.- Analog RC Polyphase Filter and Mixer Design for Large Image Rejection.- Passive Integrated RF Filters.- Integrated GHz Voltage Controlled Oscillators.
Recenzii
`The authors are to be complimented for collecting, into a single reference, a lot of interesting information related to the above mentioned topics, particularly useful for data-acquisition system designers, RF engineers, and others.'
Microelectronics Journal 29 (1998) 1039-1046
Microelectronics Journal 29 (1998) 1039-1046
Descriere
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The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.
The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.