Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method
Autor Eduard Cerny, Bachir Berkane, Pierre Girodias, Karim Khordocen Limba Engleză Paperback – 12 oct 2012
Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method presents a description methodology that was inspired by Timing Diagrams and Process Algebras, the so-called Hierarchical Annotated Diagrams. It is suitable for specifying systems with complex interface behaviors that govern the global system behavior. A HADD specification can be converted into a behavioral real-time model in VHDL and used to verify the surrounding logic, such as interface transducers. Also, function can be conservatively abstracted away and the interactions between interconnected devices can be verified using Constraint Logic Programming based on Relational Interval Arithmetic.
Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method is ofinterest to readers who are involved in defining methods and tools for system-level design specification and verification. The techniques for interface compatibility verification can be used by practicing designers, without any more sophisticated tool than a calculator.
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Specificații
ISBN-13: 9781461375692
ISBN-10: 146137569X
Pagini: 232
Ilustrații: XVI, 211 p.
Dimensiuni: 155 x 235 x 12 mm
Greutate: 0.33 kg
Ediția:Softcover reprint of the original 1st ed. 1998
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
ISBN-10: 146137569X
Pagini: 232
Ilustrații: XVI, 211 p.
Dimensiuni: 155 x 235 x 12 mm
Greutate: 0.33 kg
Ediția:Softcover reprint of the original 1st ed. 1998
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
1 Introduction.- 1.1 Digital System Design and Verification.- 1.2 Interface-Oriented Models.- 1.3 Purpose and Organization of the Book.- 2 Overview of HAAD Method.- 2.1 Leaf Action Diagrams.- 2.2 Annotations in Leaf Action Diagrams.- 2.3 Hierarchical Action Diagrams.- 2.4 Annotations in HAAD Hierarchy.- 3 Formal Characterization of HAAD.- 3.1 Leaf-Level Action Diagram Algebra.- 3.2 Verification.- 3.3 Language of Hierarchical Action Diagrams.- 3.4 Related work.- 4 HAAD VHDL Model.- 4.1 Execution of HAAD VHDL Models.- 4.2 Execution of Hierarchical Action Diagrams.- 4.3 Occurrence Time Enumeration of Output Actions.- 4.4 Enumeration and Delay Correlation.- 4.5 Organization of a HAAD Model in VHDL.- 5 Consistency, Causality and Compatibility.- 5.1 Introduction.- 5.2 Basic Concepts.- 5.3 Problems.- 5.4 BlockMachines.- 5.5 Derived Block Machines.- 5.6 Causal Action Diagrams.- 5.7 Compatibility of Action Diagrams.- 5.8 Conclusions.- 6 Interface Verification using CLP.- 6.1 Interface Timing Verification.- 6.2 Constraint Logic Programming.- 6.3 The Event Separation Problem.- 6.4 Delay Correlation.- 6.5 CSP and CLP Based on RIA.- 6.6 Solving ITV with CLP Based on RIA.- 6.7 Examples.- 6.8 Experimental Results.- 6.9 Concluding Remarks.- 7 Example: Interfacing ARM7 and a Static RAM.- 7.1 Problem Definition.- 7.2 Bus Functional Model of ARM7 Subset.- 7.3 Bus Functional Model of RAM.- 7.4 VHDL Model of interface transducer.- 7.5 Putting it all together.- 7.6 Static Interface Timing Verification.- 8 Summary and Recent Developments.- 8.1 Summary.- 8.2 Recent Developments.- 8.3 Future Directions.- References.- A Grammar of the HAAD Language.- A.1 Conventions.- A.2 Semantic Notes.- A.2.1 Generics.- A.2.2 Name Spaces.- A.2.3 Default Constraint Bounds.- A.3 Grammar Definition.- B Proofs forChapter.- B.1 Proof of Theorem 3.1.- B.2 Proof of Theorem 3.2, 3.3, 3.4, and 3.5.- B.3 Proof of Theorem 3.6.- B.4 Proof of Theorem 3.7.- B.5 Proof of Theorem 8.- B.6 Proof of Theorem 3.9.- B.7 Proof of Theorem 3.10.