High Performance Multi-Channel High-Speed I/O Circuits: Analog Circuits and Signal Processing
Autor Taehyoun Oh, Ramesh Harjanien Limba Engleză Paperback – 23 aug 2016
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Paperback (1) | 620.14 lei 6-8 săpt. | |
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Springer – 7 sep 2013 | 624.46 lei 6-8 săpt. |
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Specificații
ISBN-13: 9781493954223
ISBN-10: 1493954229
Pagini: 99
Ilustrații: X, 89 p. 64 illus., 44 illus. in color.
Dimensiuni: 155 x 235 x 5 mm
Greutate: 0.15 kg
Ediția:Softcover reprint of the original 1st ed. 2014
Editura: Springer
Colecția Springer
Seria Analog Circuits and Signal Processing
Locul publicării:New York, NY, United States
ISBN-10: 1493954229
Pagini: 99
Ilustrații: X, 89 p. 64 illus., 44 illus. in color.
Dimensiuni: 155 x 235 x 5 mm
Greutate: 0.15 kg
Ediția:Softcover reprint of the original 1st ed. 2014
Editura: Springer
Colecția Springer
Seria Analog Circuits and Signal Processing
Locul publicării:New York, NY, United States
Cuprins
Introduction.- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process.- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process.- Adaptive XTCR, AGC, and Adaptive DFE Loop.- Research Summary & Contributions.- References.- Appendix A: Noise Analysis.- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os (≥ 4).- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter.- Appendix D: Line Mismatch Sensitivity.- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench.- Appendix F: Bandwidth Improvement by Technology Scaling.
Textul de pe ultima copertă
This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.
· Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits;
· Includes critical background knowledge related to channel ISI equalization circuits;
· Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control (AGC) circuits in current I/O systems.
· Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits;
· Includes critical background knowledge related to channel ISI equalization circuits;
· Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control (AGC) circuits in current I/O systems.
Caracteristici
Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits Includes critical background knowledge related to channel ISI equalization circuits Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control (AGC) circuits in current I/O systems