Variation Tolerant On-Chip Interconnects: Analog Circuits and Signal Processing
Autor Ethiopia Enideg Nigussieen Limba Engleză Hardback – dec 2011
Toate formatele și edițiile | Preț | Express |
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Paperback (1) | 654.30 lei 6-8 săpt. | |
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Springer – dec 2011 | 607.22 lei 6-8 săpt. |
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Specificații
ISBN-13: 9781461401308
ISBN-10: 1461401305
Pagini: 184
Ilustrații: XII, 172 p.
Dimensiuni: 155 x 235 x 16 mm
Greutate: 0.44 kg
Ediția:2012
Editura: Springer
Colecția Springer
Seria Analog Circuits and Signal Processing
Locul publicării:New York, NY, United States
ISBN-10: 1461401305
Pagini: 184
Ilustrații: XII, 172 p.
Dimensiuni: 155 x 235 x 16 mm
Greutate: 0.44 kg
Ediția:2012
Editura: Springer
Colecția Springer
Seria Analog Circuits and Signal Processing
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
Introduction.- On-Chip Communication.- Interconnect Design Techniques.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.
Notă biografică
Introduction.- Interconnect Design Techniques.- On-Chip Wire Modeling.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.
Textul de pe ultima copertă
This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.
- Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect;
- Describes design techniques to mitigate problems caused by variation;
- Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.
Caracteristici
Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect Describes design techniques to mitigate problems caused by variation Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance