Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings: Lecture Notes in Computer Science, cartea 2799
Editat de Jorge Juan Chico, Enrico Maciien Limba Engleză Paperback – 3 sep 2003
Din seria Lecture Notes in Computer Science
- 20% Preț: 1005.39 lei
- 20% Preț: 322.44 lei
- 20% Preț: 324.00 lei
- 20% Preț: 315.19 lei
- 20% Preț: 238.01 lei
- 20% Preț: 554.98 lei
- 20% Preț: 322.44 lei
- 20% Preț: 438.69 lei
- 20% Preț: 325.58 lei
- 20% Preț: 148.66 lei
- 20% Preț: 310.26 lei
- 20% Preț: 256.27 lei
- 20% Preț: 1339.86 lei
- 20% Preț: 782.28 lei
- 17% Preț: 360.19 lei
- 20% Preț: 620.45 lei
- 20% Preț: 307.71 lei
- 20% Preț: 550.29 lei
- 20% Preț: 560.32 lei
- 20% Preț: 319.32 lei
- 15% Preț: 549.86 lei
- 20% Preț: 607.39 lei
- 20% Preț: 538.29 lei
- 20% Preț: 548.74 lei
- 20% Preț: 172.69 lei
- 20% Preț: 611.22 lei
- 20% Preț: 970.25 lei
- 20% Preț: 552.64 lei
- 20% Preț: 315.78 lei
- 20% Preț: 315.78 lei
- 20% Preț: 722.90 lei
- 20% Preț: 722.90 lei
- 20% Preț: 301.95 lei
- 20% Preț: 504.57 lei
- 20% Preț: 1120.51 lei
- 20% Preț: 369.12 lei
- 20% Preț: 334.94 lei
- 20% Preț: 552.64 lei
- Preț: 389.31 lei
- 20% Preț: 564.99 lei
- 20% Preț: 724.49 lei
- 20% Preț: 552.64 lei
- 20% Preț: 1018.35 lei
- 20% Preț: 331.82 lei
- 20% Preț: 309.90 lei
- 20% Preț: 122.89 lei
Preț: 621.80 lei
Preț vechi: 731.52 lei
-15% Nou
Puncte Express: 933
Preț estimativ în valută:
119.08€ • 128.86$ • 99.27£
119.08€ • 128.86$ • 99.27£
Carte tipărită la comandă
Livrare economică 09-23 decembrie
Preluare comenzi: 021 569.72.76
Specificații
ISBN-13: 9783540200741
ISBN-10: 3540200746
Pagini: 656
Ilustrații: XVII, 631 p.
Dimensiuni: 155 x 233 x 34 mm
Greutate: 0.86 kg
Ediția:2003
Editura: Springer Berlin, Heidelberg
Colecția Springer
Seria Lecture Notes in Computer Science
Locul publicării:Berlin, Heidelberg, Germany
ISBN-10: 3540200746
Pagini: 656
Ilustrații: XVII, 631 p.
Dimensiuni: 155 x 233 x 34 mm
Greutate: 0.86 kg
Ediția:2003
Editura: Springer Berlin, Heidelberg
Colecția Springer
Seria Lecture Notes in Computer Science
Locul publicării:Berlin, Heidelberg, Germany
Public țintă
ResearchCuprins
Keynote Speech.- Architectural Challenges for the Next Decade Integrated Platforms.- Gate-Level Modeling and Design.- Analysis of High-Speed Logic Families.- Low Voltage, Double-Edge-Triggered Flip Flop.- A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems.- State Encoding for Low-Power FSMs in FPGA.- Low Level Modeling and Characterization.- Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies.- A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates.- CMOS Gate Sizing under Delay Constraint.- Process Characterisation for Low VTH and Low Power Design.- Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results.- Interconnect Modeling and Optimization.- Effects of Temperature in Deep-Submicron Global Interconnect Optimization.- Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits.- Estimation of Crosstalk Noise for On-Chip Buses.- A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization.- Interconnect Driven Low Power High-Level Synthesis.- Asynchronous Techniques.- Bridging Clock Domains by Synchronizing the Mice in the Mousetrap.- Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization.- New GALS Technique for Datapath Architectures.- Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders.- Static Implementation of QDI Asynchronous Primitives.- Keynote Speech.- The Emergence of Design for Energy Efficiency: An EDA Perspective.- Industrial Session.- The Most Complete Mixed-Signal Simulation Solution with ADVance MS.- Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips.- Power Management in Synopsys Galaxy Design Platform.- Open Multimedia Platform for Next-Generation Mobile Devices.- RTL Power Modeling and Memory Optimisation.- Statistical Power Estimation of Behavioral Descriptions.- A Statistical Power Model for Non-synthetic RTL Operators.- Energy Efficient Register Renaming.- Stand-by Power Reduction for Storage Circuits.- A Unified Framework for Power-Aware Design of Embedded Systems.- High-Level Modeling.- A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems.- High-Level Area and Current Estimation.- Switching Activity Estimation in Non-linear Architectures.- Instruction Level Energy Modeling for Pipelined Processors.- Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level.- Power Efficient Technologies and Designs.- An Adiabatic Charge Pump Based Charge Recycling Design Style.- Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing.- Low-Power Response Time Accelerator with Full Resolution for LCD Panel.- Memory Compaction and Power Optimization for Wavelet-Based Coders.- Design Space Exploration and Trade-Offs in Analog Amplifier Design.- Keynote Speech.- Power and Timing Driven Physical Design Automation.- Communication Modeling and Design.- Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks.- Remote Power Control of Wireless Network Interfaces.- Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders.- A Fully Digital Numerical-Controlled-Oscillator.- Low Power Issues in Processors and Multimedia.- Energy Optimization of High-Performance Circuits.- Instruction Buffering Exploration for Low Energy Embedded Processors.- Power-Aware Branch Predictor Update for High-Performance Processors.- Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms.- High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder.- Poster Session 1.- Metric Definition for Circuit Speed Optimization.- Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies.- An Asynchronous Viterbi Decoder for Low-Power Applications.- Analysis of the Contribution of Interconnect Effects in Energy Dissipation of VLSI Circuits.- A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application.- Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.- Poster Session 2.- A Practical ASIC Methodology for Flexible Clock Tree Synthesis with Routing Blockages.- Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus.- Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction.- A Bottom-Up Approach to On-Chip Signal Integrity.- Advanced Cell Modeling Techniques Based on Polynomial Expressions.- RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches.- Poster Session 3.- Data Dependences Critical Path Evaluation at C/C++ System Level Description.- A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements.- Consideration of Control System and Memory Contributions in Practical Resource-Constrained Scheduling for Low Power.- Low-Power Cache with Successive Tag Comparison Algorithm.- FPGA Architecture Design and Toolset for Logic Implementation.- Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.
Caracteristici
Includes supplementary material: sn.pub/extras