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IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection de Khaled Salah Mohamed

IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection: Analog Circuits and Signal Processing

Autor Khaled Salah Mohamed
en Limba Engleză Hardback – 8 sep 2015
This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including  those associated with many of the most common memory cores, controller IPs  and system-on-chip (SoC) buses. Readers will also benefit from the author’s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain.  A SoC case study is presented to compare traditional verification with the new verification methodologies.
Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection;
Introduce a deep introduction for Verilog for both implementation and verification point of view. 
Demonstrates how to use IP in applications such as memory controllers and SoC buses.
Describes a new verification methodology called bug localization;
Presents a novel scan-chain methodology for RTL debugging;
Enables readers to employ UVM methodology in straightforward, practical terms.
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Specificații

ISBN-13: 9783319220345
ISBN-10: 3319220349
Pagini: 154
Ilustrații: IX, 154 p.
Dimensiuni: 155 x 235 x 15 mm
Greutate: 0.41 kg
Ediția:1st ed. 2016
Editura: Springer International Publishing
Colecția Springer
Seria Analog Circuits and Signal Processing

Locul publicării:Cham, Switzerland

Public țintă

Professional/practitioner

Cuprins

1. Introduction.- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection.- 3. Analyzing the Trade-off between Different Memory Cores and Controllers.- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES.- 5. Verilog for Implementation and Verification.- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation.- 7. Conclusions.

Notă biografică

Dr. Khaled Salah attended the school of engineering, Department of Electronics and Communications at Ain-Shams University, Egypt, from 1998 to 2003, where he received his B.Sc. degree in Electronics and Communications Engineering with distinction and honor degree. He received his M.Sc. and his Ph.D. degrees in Electronics and Communications in 2008, 2012 respectively. He joined Mentor Graphic Corporation, where he designed many SoC IPs such as AHB, HDMI, HDCP, eMMC, SDcard, HMC. Currently, Dr. Khaled Salah is a Technical Lead at the Emulation division at Mentor Graphic, Egypt. Dr. Khaled Salah has published one book and more than 42 research papers in the top refereed journals and conferences. His research interests are in 3D integration, IP Modeling, and SoC design.

Textul de pe ultima copertă

This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including  those associated with many of the most common memory cores, controller IPs  and system-on-chip (SoC) buses. Readers will also benefit from the author’s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain.  A SoC case study is presented to compare traditional verification with the new verification methodologies.
·         Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection;
·         Introduce a deep introduction for Verilog for both implementation and verification point of view. 
·         Demonstrates how to use IP in applications such as memory controllers and SoC buses.
·         Describes a new verification methodology called bug localization;
·         Presents a novel scan-chain methodology for RTL debugging;
·         Enables readers to employ UVM methodology in straightforward, practical terms.

Caracteristici

Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection Describes a new verification methodology called bug localization Presents a novel scan-chain methodology for RTL debugging Enables readers to employ UVM methodology in straightforward, practical terms Demonstrates how to use IP in applications such as memory controllers and SoC buses