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Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs de Sven Goossens

Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs: Embedded Systems

Autor Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens
en Limba Engleză Paperback – 22 apr 2018
This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.
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Specificații

ISBN-13: 9783319811963
ISBN-10: 3319811967
Ilustrații: XXVII, 202 p. 78 illus. in color.
Dimensiuni: 155 x 235 mm
Greutate: 0.33 kg
Ediția:Softcover reprint of the original 1st ed. 2016
Editura: Springer International Publishing
Colecția Springer
Seria Embedded Systems

Locul publicării:Cham, Switzerland

Cuprins

Introduction.-Reconfigurable Real-Time Memory Controller Architecture.- Memory Patterns.- Cycle-AccurateSDRAM Power Modeling.- Power/Performance Trade-Offs.- Conservative Open-PagePolicy.- Reconfiguration.- Related Work.- Conclusions and Future Work.- Appendix A: ILP Problem Formation.- AppendixB: Memory Specifications.- Appendix C: Code Listings.- Appendix D: List ofAcronyms.- Appendix E: List of Symbols.

Notă biografică

Sven Goossens receivedhis M.Sc. in Embedded Systems from the Eindhoven University of Technology in2010. He worked as a researcher in the Electrical Engineering of the sameuniversity until 2011, and then started as a Ph.D. student, graduating in 2015.He is currently employed as a Hardware Architect at Intrinsic-ID. His researchinterests include mixed time-criticality systems, composability and SDRAMcontrollers.
Karthik Chandrasekar earnedhis M.Sc. degree in Computer Engineering from TU Delft in the Netherlands inNovember 2009. In October 2014, he received his Ph.D. also from the sameuniversity. His research interests include SoC Architectures,DRAM memories & memory controllers, on-chip communication networks andperformance & power modeling and analysis. He is currently employed as aSenior Architect at Nvidia.
Benny Akesson receivedhis M.Sc. degree at Lund Institute of Technology, Sweden in 2005 and a Ph.D.from Eindhoven University of Technology, the Netherlands in 2010. Since then,he has been employed as a Researcher at Eindhoven University of Technology, CzechTechnical University in Prague, and CISTER/INESC TEC ResearchUnit in Porto. Currently, he is working as a Research Fellow at TNO-ESI.His research interests include memory controller architectures, real-timescheduling, performance modeling, and performance virtualization. He haspublished more than 50 peer-reviewed conference papers and journal articles, aswell as two books about memory controllers for real-time embedded systems.

Kees Goossens receivedhis Ph.D. in Computer Science from the University of Edinburgh in 1993. Heworked for Philips/NXP Research from 1995 to 2010 on networks-onchips for consumerelectronics, where real-time performance, predictability, and costs are majorconstraints. He was part-time professor at Delft University from 2007 to 2010, andis now full professor at the Eindhoven University of Technology, where hisresearch focuses on composable (virtualized), predictable (real-time),low-power embedded systems, supporting multiple models of computation. Hepublished 4 books, 100+ papers, and 24 patents.

Textul de pe ultima copertă

This book discusses thedesign and performance analysis of SDRAM controllers that cater to bothreal-time and best-effort applications, i.e. mixed-time-criticality memorycontrollers. The authors describe the state of the art, and then focus on anarchitecture template for reconfigurable memory controllers that addresseseffectively the quickly evolving set of SDRAM standards, in terms of worst-casetiming and power analysis, as well as implementation. A prototypeimplementation of the controller in SystemC and synthesizable VHDL for an FPGAdevelopment board are used as a proof of concept of the architecture template.

Caracteristici

Discusses power-constrained mixed-time-criticality systems and why they are complex to design and verify Explains the concepts of predictability and composability and how they address the design and verification challenges of mixed-time-criticality systems Provides an overview of the requirements of memory controllers in power-constrained mixed-time-criticality systems and discusses why current memory controllers struggle to satisfy them Includes supplementary material: sn.pub/extras