Cantitate/Preț
Produs
Total produse
Vezi coșul
Minimizing and Exploiting Leakage in VLSI Design de Nikhil Jayakumar

Minimizing and Exploiting Leakage in VLSI Design

Autor Nikhil Jayakumar, Suganth Paul, Rajesh Garg
en Limba Engleză Paperback – 28 noi 2014
Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic.
Citește tot Restrânge

Toate formatele și edițiile

Toate formatele și edițiile Preț Express
Paperback (1) 68018 lei  6-8 săpt.
  Springer Us – 28 noi 2014 68018 lei  6-8 săpt.
Hardback (1) 92877 lei  6-8 săpt.
  Springer Us – 3 dec 2009 92877 lei  6-8 săpt.

Preț: 68018 lei

Preț vechi: 80021 lei
-15% Nou

Puncte Express: 1020
Preț estimativ în valută:
13019€ • 13532$ • 10784£

Carte tipărită la comandă

Livrare economică 05-19 februarie 25

 Adaugă în coș

Wish list
Gift list
Am citit!
Adaugă în listă
Preluare comenzi: 021 569.72.76

Specificații

ISBN-13: 9781489985293
ISBN-10: 1489985298
Pagini: 244
Ilustrații: XXVII, 214 p.
Dimensiuni: 155 x 235 x 13 mm
Greutate: 0.35 kg
Ediția:2010
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States

Public țintă

Research

Cuprins

Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes.- Existing Leakage Minimization Approaches.- Computing Leakage Current Distributions.- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities.- The HL Approach: A Low-Leakage ASIC Design Methodology.- Simultaneous Input Vector Control and Circuit Modification.- Optimum Reverse Body Biasing for Leakage Minimization.- I: Conclusions and Future Directions.- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design.- Exploiting Leakage: Sub-threshold Circuit Design.- Adaptive Body Biasing to Compensate for PVT Variations.- Optimum VDD for Minimum Energy.- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining.- II: Conclusions and Future Directions.- Design of a Sub-threshold BFSK Transmitter IC.- Design of the Chip.- Implementation of the Chip.- Experimental Results.

Textul de pe ultima copertă

Minimizing and Exploiting Leakage in VLSI Design
Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri
Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs.
This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book.
  • Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage.
  • Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design.
  • Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes).

Caracteristici

Provides a variety of approaches to control and exploit leakage Examines the issues with implementing sub-threshold logic and describes techniques to tackle these issues Presents a new, practical self-compensated, closed loop approach to controlling leakage, via sub-threshold circuits, which yields upwards of 20X power savings