Cantitate/Preț
Produs
Total produse
Vezi coșul
Pipelined ADC Design and Enhancement Techniques de Imran Ahmed

Pipelined ADC Design and Enhancement Techniques: Analog Circuits and Signal Processing

Autor Imran Ahmed
en Limba Engleză Paperback – 5 mai 2012
Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.
Citește tot Restrânge

Toate formatele și edițiile

Toate formatele și edițiile Preț Express
Paperback (1) 94182 lei  6-8 săpt.
  SPRINGER NETHERLANDS – 5 mai 2012 94182 lei  6-8 săpt.
Hardback (1) 94785 lei  6-8 săpt.
  SPRINGER NETHERLANDS – 19 mar 2010 94785 lei  6-8 săpt.

Din seria Analog Circuits and Signal Processing

Preț: 94182 lei

Preț vechi: 114856 lei
-18% Nou

Puncte Express: 1413
Preț estimativ în valută:
18022€ • 18864$ • 149100£

Carte tipărită la comandă

Livrare economică 31 martie-14 aprilie

 Adaugă în coș

Wish list
Gift list
Am citit!
Adaugă în listă
Preluare comenzi: 021 569.72.76

Specificații

ISBN-13: 9789400731790
ISBN-10: 9400731795
Pagini: 240
Ilustrații: XXV, 200 p.
Dimensiuni: 155 x 235 x 13 mm
Greutate: 0.34 kg
Ediția:2010
Editura: SPRINGER NETHERLANDS
Colecția Springer
Seria Analog Circuits and Signal Processing

Locul publicării:Dordrecht, Netherlands

Public țintă

Research

Cuprins

Pipelined ADC Design.- ADC Architectures.- Pipelined ADC Architecture Overview.- Scaling Power with Sampling Rate in an ADC.- State of the Art Pipelined ADC Design.- Pipelined ADC Enhancement Techniques.- Rapid Calibration of DAC and Gain Errors in a Multi-bit Pipeline Stage.- A Power Scalable and Low Power Pipelined ADC.- A Sub-sampling ADC with Embedded Sample-and-Hold.- A Capacitive Charge Pump Based Low Power Pipelined ADC.- Summary.

Textul de pe ultima copertă

Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs. Written for both researchers and professionals, Pipelined ADC Design and Enhancement Techniques provides:
i.) A tutorial discussion, for those new to pipelined ADCs, of the basic design and tradeoffs involved in designing a pipelined ADC
ii.) A detailed discussion of four novel silicon tested pipelined ADC topologies geared towards those looking to gain insight into state-of-the-art design in the area. The ADCs detailed include:
- An 11-bit 45MS/s ADC which rapidly digitally calibrates in the background both DAC and gain errors
- A 10-bit ADC with power scalable between 50MS/s (35mW) to 1kS/s (15µW)
- A 10-bit ADC for use in sub-sampled systems with a technique to eliminate the front-end sample-and-hold
- A 10-bit, 50MS/s ADC which uses a capacitive charge pump based approach to enable a very small power consumption of 9.9mW.

Caracteristici

Based on award winning and practical works published at ISSCC and ESSCIRC. The fact that the ideas discussed in the book have already been vetted by a high calibre peer-review ensures the reader will be getting premium content Discusses many approaches used to enable very low power consumption; an area of interest for 'green' electronics Enables the reader to gain both tutorial and detailed insight into state-of-the-art pipelined ADCs from one source Includes supplementary material: sn.pub/extras