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Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling de Ayan Mandal

Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling

Autor Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra
en Limba Engleză Paperback – 23 aug 2016
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
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Specificații

ISBN-13: 9781493948178
ISBN-10: 1493948172
Pagini: 156
Ilustrații: XIII, 143 p. 95 illus., 10 illus. in color.
Dimensiuni: 155 x 235 x 9 mm
Greutate: 0.23 kg
Ediția:Softcover reprint of the original 1st ed. 2014
Editura: Springer
Colecția Springer
Locul publicării:New York, NY, United States

Cuprins

Introduction.- Clock Distribution for fast Networks-on-Chip.- Fast Network-on-Chip Design.- Fast On-Chip Data transfer using Sinusoid Signals.- Conclusion and Future Work.

Textul de pe ultima copertă

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
 
• Describes novel methods for high-speed network-on-chip (NoC) design;
• Enables readers to understand NoC design from both circuit and architectural levels;
• Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC;
• Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

Caracteristici

Describes novel methods for high-speed network-on-chip (NoC) design Enables readers to understand NoC design from both circuit and architectural levels Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art Includes supplementary material: sn.pub/extras