Planar Double-Gate Transistor: From technology to circuit
Editat de Amara Amara, Olivier Rozeauen Limba Engleză Paperback – 19 oct 2010
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Specificații
ISBN-13: 9789048181087
ISBN-10: 9048181089
Pagini: 220
Ilustrații: VIII, 211 p.
Dimensiuni: 155 x 235 x 12 mm
Greutate: 0.31 kg
Ediția:Softcover reprint of hardcover 1st ed. 2009
Editura: SPRINGER NETHERLANDS
Colecția Springer
Locul publicării:Dordrecht, Netherlands
ISBN-10: 9048181089
Pagini: 220
Ilustrații: VIII, 211 p.
Dimensiuni: 155 x 235 x 12 mm
Greutate: 0.31 kg
Ediția:Softcover reprint of hardcover 1st ed. 2009
Editura: SPRINGER NETHERLANDS
Colecția Springer
Locul publicării:Dordrecht, Netherlands
Public țintă
ResearchCuprins
Multiple Gate Technologies.- Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach.- Compact Modeling of Double Gate MOSFET for IC Design.- Low Frequency Noise in Double-Gate SOI CMOS Devices.- Analog Circuit Design.- Logic Circuit Design with DGMOS Devices.- SRAM Circuit Design.
Textul de pe ultima copertă
This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring.
Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap.
The book topics are mainly focusing on:
Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap.
The book topics are mainly focusing on:
- Detailed description of specific processes that allow the optimization of the CMOS IPDGT device
- CMOS IPDGT modeling, both compact and physical models are presented
- Device characterization
- Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates.
Caracteristici
First book dealing with Technology and Design Interaction Presents a cross-disciplinary based approach to optimize a new and complex technology Covers all aspects of IC Design with advanced technologies: process, device modelling, characterization, and circuit design of analogue, digital and memory circuits Introduces new circuit concepts taking benefit of the double-gate device structures