3D Integration for NoC-based SoC Architectures: Integrated Circuits and Systems
Editat de Abbas Sheibanyrad, Frédéric Pétrot, Axel Jantschen Limba Engleză Paperback – 27 dec 2012
Toate formatele și edițiile | Preț | Express |
---|---|---|
Paperback (1) | 684.77 lei 6-8 săpt. | |
Springer – 27 dec 2012 | 684.77 lei 6-8 săpt. | |
Hardback (1) | 934.19 lei 6-8 săpt. | |
Springer – 10 dec 2010 | 934.19 lei 6-8 săpt. |
Din seria Integrated Circuits and Systems
- 15% Preț: 647.16 lei
- 18% Preț: 1365.20 lei
- 15% Preț: 630.91 lei
- 18% Preț: 1192.99 lei
- 18% Preț: 938.35 lei
- 15% Preț: 639.91 lei
- 20% Preț: 971.48 lei
- 18% Preț: 936.02 lei
- 18% Preț: 934.49 lei
- 18% Preț: 934.19 lei
- 18% Preț: 937.74 lei
- 24% Preț: 805.38 lei
- 20% Preț: 980.55 lei
- 15% Preț: 623.32 lei
- 18% Preț: 933.22 lei
- 20% Preț: 632.79 lei
- 18% Preț: 1206.64 lei
- 24% Preț: 803.80 lei
- 15% Preț: 638.91 lei
- 18% Preț: 768.44 lei
- 18% Preț: 984.43 lei
- 15% Preț: 624.63 lei
- 15% Preț: 683.48 lei
- 18% Preț: 925.18 lei
- 15% Preț: 630.60 lei
- 18% Preț: 870.69 lei
- 18% Preț: 930.90 lei
- 18% Preț: 928.43 lei
- 15% Preț: 623.49 lei
- 18% Preț: 940.16 lei
- 18% Preț: 928.74 lei
- 18% Preț: 925.18 lei
- 18% Preț: 926.86 lei
- 18% Preț: 937.13 lei
- 15% Preț: 624.63 lei
- 23% Preț: 570.64 lei
- 18% Preț: 936.81 lei
Preț: 684.77 lei
Preț vechi: 805.61 lei
-15% Nou
Puncte Express: 1027
Preț estimativ în valută:
131.05€ • 136.53$ • 108.96£
131.05€ • 136.53$ • 108.96£
Carte tipărită la comandă
Livrare economică 08-22 februarie 25
Preluare comenzi: 021 569.72.76
Specificații
ISBN-13: 9781461427483
ISBN-10: 1461427487
Pagini: 288
Ilustrații: X, 278 p.
Dimensiuni: 155 x 235 x 15 mm
Greutate: 0.41 kg
Ediția:2011
Editura: Springer
Colecția Springer
Seria Integrated Circuits and Systems
Locul publicării:New York, NY, United States
ISBN-10: 1461427487
Pagini: 288
Ilustrații: X, 278 p.
Dimensiuni: 155 x 235 x 15 mm
Greutate: 0.41 kg
Ediția:2011
Editura: Springer
Colecția Springer
Seria Integrated Circuits and Systems
Locul publicării:New York, NY, United States
Public țintă
Professional/practitionerCuprins
Three-Dimensional Integration of Integrated Circuits - an Introduction.- The Promises and Limitation of 3-D Integration.- Testing 3D Stacked ICs Containing Through-Silicon Vias.- Design and Computer Aided Design of 3DIC.- Physical Analysis of NoC Topologies for 3-D Integrated Systems.- Three-Dimensional Networks-on-Chip: Performance Evaluation.- Asynchronous 3D-NoCs.- Design of Application-Specific 3D Networks-on-Chip Architectures.- 3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks.- 3-D NoC on Inductive Wireless Interconnect.- Influence of Stacked 3D Memory/Cache architectures on GPUs.
Textul de pe ultima copertă
Back Cover CopySERIES:Integrated Circuits and Systems 3D-Integration for NoC-based SoC Architectures by: (Editors)Abbas Sheibanyrad Frédéric Petrot Axel Janstch This book investigates on the promises, challenges, and solutions for the 3D Integration (vertically stacking) of embedded systems connected via a network on a chip. It covers the entire architectural design approach for 3D-SoCs. 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures have emerged as topics critical for current R&D leading to a broad range of products. This book presents a comprehensive, system-level overview of three-dimensional architectures and micro-architectures. •Presents a comprehensive, system-level overview of three-dimensional architectures and micro-architectures; •Covers the entire architectural design approach for 3D-SoCs;•Includes state-of-the-art treatment of 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures.
Caracteristici
Provides a detailed background on the state of error control methods for on-chip interconnects, including Error Control Coding, Double Sampling, and On-Line Testing Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links Presents techniques for managing intermittent and permanent errors using a non-interrupting in-line test method with spare wire replacement Includes supplementary material: sn.pub/extras