Wafer Level 3-D ICs Process Technology: Integrated Circuits and Systems
Editat de Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reifen Limba Engleză Hardback – 19 sep 2008
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Specificații
ISBN-13: 9780387765327
ISBN-10: 0387765328
Pagini: 410
Ilustrații: XII, 410 p.
Dimensiuni: 155 x 235 x 23 mm
Greutate: 0.66 kg
Ediția:2009
Editura: Springer Us
Colecția Springer
Seria Integrated Circuits and Systems
Locul publicării:New York, NY, United States
ISBN-10: 0387765328
Pagini: 410
Ilustrații: XII, 410 p.
Dimensiuni: 155 x 235 x 23 mm
Greutate: 0.66 kg
Ediția:2009
Editura: Springer Us
Colecția Springer
Seria Integrated Circuits and Systems
Locul publicării:New York, NY, United States
Public țintă
Professional/practitionerCuprins
Overview of Wafer-Level 3D ICs.- Monolithic 3D Integrated Circuits.- Stacked CMOS Technologies.- Wafer-Bonding Technologies and Strategies for 3D ICs.- Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies.- Cu Wafer Bonding for 3D IC Applications.- Cu/Sn Solid#x2013;Liquid Interdiffusion Bonding.- An SOI-Based 3D Circuit Integration Technology.- 3D Fabrication Options for High-Performance CMOS Technology.- 3D Integration Based upon Dielectric Adhesive Bonding.- Direct Hybrid Bonding.- 3D Memory.- Circuit Architectures for 3D Integration.- Thermal Challenges of 3D ICs.- Status and Outlook.
Textul de pe ultima copertă
Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration.
Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration.
Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration.
Caracteristici
Focuses on the foundry-based process technology for the fabrication of 3-D ICs Discusses the technology platform for pre-packaging wafer level 3-D ICs Includes chapters contributed by various experts in the field of wafer-level 3-D ICs process technology