Test Resource Partitioning for System-on-a-Chip: Frontiers in Electronic Testing, cartea 20
Autor Vikram Iyengar, Anshuman Chandraen Limba Engleză Hardback – 30 iun 2002
SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols.
Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume.
Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.
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Paperback (1) | 638.11 lei 6-8 săpt. | |
Springer Us – 7 noi 2012 | 638.11 lei 6-8 săpt. | |
Hardback (1) | 644.49 lei 6-8 săpt. | |
Springer Us – 30 iun 2002 | 644.49 lei 6-8 săpt. |
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Specificații
ISBN-13: 9781402071195
ISBN-10: 1402071191
Pagini: 232
Ilustrații: XII, 232 p.
Dimensiuni: 155 x 235 x 21 mm
Greutate: 0.53 kg
Ediția:2002
Editura: Springer Us
Colecția Springer
Seria Frontiers in Electronic Testing
Locul publicării:New York, NY, United States
ISBN-10: 1402071191
Pagini: 232
Ilustrații: XII, 232 p.
Dimensiuni: 155 x 235 x 21 mm
Greutate: 0.53 kg
Ediția:2002
Editura: Springer Us
Colecția Springer
Seria Frontiers in Electronic Testing
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
1. Test Resource Partitioning.- 2. Test Access Mechanism Optimization.- 3. Improved Test Bus Partitioning.- 4. Test Wrapper And TAM Co-Optimization.- 5. Test Scheduling.- 6. Precedence, Preemption, And Power Constraints.- 7. Test Data Compression Using Golomb Codes.- 8. Frequency-Directed Run-Length (FDR) Codes.- 9. TRP for Low-Power Scan Testing.- 10. Conclusion.- References.